AD7393AN Analog Devices, AD7393AN Datasheet - Page 8

• Manufacturer Part Number: AD7393AN
• Description: +3 V/ Parallel Input Micropower 10- and 12-Bit DACs
• Manufacturer: Analog Devices

AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. The op amp has a 60 s typical
settling time to 0.1% of full scale. There are slight differences in
settling time for negative slewing signals versus positive. Also,
negative transition settling-time to within the last 6 LSBs of
zero volts has an extended settling time. The rail-to-rail output
stage of this amplifier has been designed to provide precision
performance while operating near either power supply. Figure
25 shows an equivalent output schematic of the rail-to-rail-
amplifier with its N-channel pull-down FETs that will pull an
output load directly to GND. The output sourcing current is
provided by a P-channel pull-up device that can source current
to GND terminated loads.
The rail-to-rail output stage provides 1 mA of output current.
The N-channel output pull-down MOSFET, shown in Figure
25, has a 35
near ground. In addition to resistive load driving capability, the
amplifier also has been carefully designed and characterized for
up to 100 pF capacitive load driving capability.
REFERENCE INPUT
The reference input terminal has a constant input resistance
independent of digital code, which results in reduced glitches
on the external reference voltage source. The high 2.5 M
input-resistance minimizes power dissipation within the
AD7392/AD7393 D/A converters. The V
input voltages ranging from ground to the positive-supply volt-
age V
reference voltage source is connection of the REF terminal to
the positive V
voltage output span maximizing the programmed range. The
reference input will accept ac signals as long as they are kept
within the supply voltage range, 0 < V
ence bandwidth and integral nonlinearity error performance are
plotted in the typical performance section (see Figures 20 and
21). The ratiometric reference feature makes the AD7392/
AD7393 an ideal companion to ratiometric analog-to-digital
converters such as the AD7896.
POWER SUPPLY
The very low power consumption of the AD7392/AD7393 is a
direct result of a circuit design optimizing the use of a CBCMOS
process. By using the low power characteristics of CMOS for
the logic and the low noise, tight-matching of the complemen-
tary bipolar transistors, excellent analog accuracy is achieved.
One advantage of the rail-to-rail output amplifiers used in the
AD7392/AD7393 is the wide range of usable supply voltage.
The part is fully specified and tested for operation from +2.7 V
to +5.5 V.
AD7392/AD7393
DD
Figure 25. Equivalent Analog Output Circuit
. One of the simplest applications that saves an external
DD
ON resistance that sets the sink current capability
supply. This connection results in a rail-to-rail
P-CH
N-CH
REF IN
REF
V
< V
V
AGND
input accepts
OUT
DD
DD
. The refer-
–8–
POWER SUPPLY BYPASSING AND GROUNDING
Precision analog products, such as the AD7392/AD7393, require a
well filtered power source. Since the AD7392/AD7393 oper-
ate from a single +3 V to +5 V supply, it seems convenient to
simply tap into the digital logic power supply. Unfortunately,
the logic supply is often a switch-mode design, which generates
noise in the 20 kHz to 1 MHz range. In addition, fast logic gates
can generate glitches of hundreds of millivolts in amplitude due
to wiring resistance and inductance. The power supply noise
generated as a result means that special care must be taken to
assure that the inherent precision of the DAC is maintained.
Good engineering judgment should be exercised when address-
ing the power supply grounding and bypassing of the AD7392.
The AD7392 should be powered directly from the system power
supply. This arrangement, shown in Figure 26, employs an LC
filter and separate power and ground connections to isolate the
analog section from the logic switching transients.
Figure 26. Use Separate Traces to Reduce Power Supply
Noise
Whether or not a separate power supply trace is available, gener-
ous supply bypassing will reduce supply line induced errors.
Local supply bypassing, consisting of a 10 F tantalum electro-
lytic in parallel with a 0.1 F ceramic capacitor, is recom-
mended in all applications (Figure 27).
Figure 27. Recommended Supply Bypassing for the
AD7392/AD7393
TTL/CMOS
CIRCUITS
LOGIC
POWER SUPPLY
DB0–DB11
* OPTIONAL EXTERNAL
REFERENCE BYPASS
SHDN
+5V
RS
CS
*
C
2
3
4
FERRITE BEAD:
2 TURNS, FAIR-RITE
#2677006301
REF
20
AD7392
AD7393
GND
OR
+2.7V TO +5.5V
17, 18
100 F
ELECT.
V
DD
1
19
10-22 F
TANT.
0.1 F
0.1 F
CER.
10 F
V
+5V
OUT
+5V
RETURN
REV. A