ICS1893 Integrated Circuit Systems, ICS1893 Datasheet - Page 71

• Manufacturer Part Number: ICS1893
• Description: 3.3-V 10Base-T/100Base-TX Integrated PHYceiver
• Manufacturer: Integrated Circuit Systems

8.3.11 Link Status (bit 1.2)
8.3.12 Jabber Detect (bit 1.1)
8.3.13 Extended Capability (bit 1.0)
ICS1893 Rev C 6/6/00
The purpose of this bit 1.2 (which is also accessible through the QuickPoll Detailed Status Register, bit
17.0) is to determine if an established link is dropped, even momentarily. To indicate a link that is:
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•
This bit is a latching low (LL) bit that the Link Monitor function controls. (For more information on latching
high and latching low bits, see
Bits”
100Base-TX Twisted-Pair Receivers to determine the link status and stores the results in the Link Status
bit.
The criterion the Link Monitor uses to determine if a link is valid or invalid depends on the following:
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•
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For more information on the Link Monitor Function (relative to the Link Status bit), see
“ 10Base-T Operation: Link Monitor”
The purpose of this bit is to allow an STA to determine if the ICS1893 detects a Jabber condition as defined
in the ISO/IEC specification.The ICS1893 Jabber Detection function is controlled by the Jabber Inhibit bit in
the 10Base-T Operations register (bit 18.5). To detect a Jabber condition, first the ICS1893 Jabber
Detection function must be enabled. When bit 18.5 is logic:
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•
Note:
1. The Jabber Detect bit is accessible through both the Status register (as bit 1.1) and the QuickPoll
2. The Jabber Detect bit is a latching high (LH) bit. (For more information on latching high and latching low
The STA reads bit 1.0 to determine if the ICS1893 has an extended register set. In the ICS1893 this bit is
always logic one, indicating that it has extended registers.
Valid, the ICS1893 sets bit 1.2 to logic one.
Invalid, the ICS1893 clears bit 1.2 to logic zero.
Type of link
Present link state (valid or invalid)
Presence of any link errors
Auto-negotiation process
Zero, the ICS1893 disables Jabber Detection and sets the Jabber Detect bit to logic zero.
One, the ICS1893 enables Jabber Detection and sets the Jabber Detect bit to logic one upon detection
of a Jabber condition. When no Jabber condition is detected, the Jabber Detect bit is not altered.
ICS1893 - Release
Detailed Status Register (as bit 17.2). A read of either register clears the Jabber Detect bit.
bits, see
.) The Link Monitor function continually observes the data received by either its 10Base-T or
Section 8.1.4.1, “ Latching High Bits”
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Section 8.1.4.1, “ Latching High Bits”
.
71
and
Section 8.1.4.2, “ Latching Low Bits”
and
Chapter 8 Management Register Set
Section 8.1.4.2, “ Latching Low
Section 7.5.5,
.)
June, 2000