AD744 Analog Devices, AD744 Datasheet - Page 10

• Manufacturer Part Number: AD744
• Description: Precision/ 500 ns Settling BiFET Op Amp
• Manufacturer: Analog Devices

AD744
HIGH-SPEED OP AMP APPLICATIONS
AND TECHNIQUES
DAC Buffers (I-to-V Converters)
Digital-to-analog converters which use bipolar transistors to
switch currents into (or out of) their outputs can achieve very
fast settling times. The AD565A, for example, is specified to
settle to 12 bits in less than 250 ns, with a current output. How-
ever, in many applications, a voltage output is desirable, and it
would be useful – perhaps essential – that this I-to-V conversion
be accomplished without increasing the settling time or without
degrading the accuracy of the DAC.
Figure 34 is a schematic of an AD565A DAC using an AD744
output buffer. The 10 pF C
DAC’s output capacitance, plus the 5.5 pF amplifier input
capacitance.
Figure 35 is an oscilloscope photo of the AD744’s output volt-
age with a +10 V to 0 V step applied; this corresponds to an all
“1s” to all “0s” code change on the DAC. Since the DAC is
connected in the 20 V span mode, 1 LSB is equal to 4.88 mV.
Output settling time for the AD565/AD744 combination is less
than 500 ns to within a 2.44 mV, 1/2 LSB error band.
ADJUST
LEAD
100
GAIN
capacitor compensates for the
GND
±
REF
REF
IN
0.1 F
OUT
REF
–V
19.95k
20k
10V
EE
POWER
GND
V
CC
0.1 F
AD565A
MSB
9.96k
100
LSB
BIPOLAR
OFFSET
ADJUST
A HIGH-SPEED, 3 OP AMP INSTRUMENTATION
AMPLIFIER CIRCUIT
The instrumentation amplifier circuit shown in Figure 36 can
provide a range of gains from unity up to 1000 and higher. The
circuit bandwidth is 4 MHz at a gain of 1 and 750 kHz at a gain
of 10; settling time for the entire circuit is less than 2 µs
to within 0.01% for a 10 V step, (G = 10).
While the AD744 is not stable with 100% negative feedback (as
when connected as a standard voltage follower), phase margin
and therefore stability at unity gain may be increased to an accept-
able level by placing the parallel combination of a resistor and a
small lead capacitor between each amplifier’s output and its
inverting input terminal.
The only penalty associated with this method is a small band-
width reduction at low gains. The optimum value for C
may be determined from the graph of Figure 41. This technique
can be used in the circuit of Figure 36 to achieve stable opera-
tion at gains from unity to over 1000.
5k
5k
8k
+IN
–IN
COMM
+15V
–15V
R
G
10V SPAN
DAC OUT
20V SPAN
FOR OPTIONAL OFFSET ADJUSTMENT:
TRIM A1, A3 USING TRIM PROCEDURE SHOWN IN FIGURE 21.
VOLTRONICS SP20 TRIMMER CAPACITOR OR EQUIVALENT
RATIO MATCHED 1% METAL FILM RESISTORS
7.5pF
7.5pF
CIRCUIT GAIN =
A2
A1
AD744
AD744
1 F
1 F
10k
10k
C
10pF
LEAD
+V
–V
AD744
S
S
+15V
–15V
10k
10k
(TRIM FOR BEST SETTLING TIME)
20,000
5pF
R
1 F
G
1 F
+ 1
1 F
1 F
1.5pF – 20pF
10k
10k
A3
AD744
0.1 F
0.1 F
EACH
AMPLIFIER
PIN 7
PIN 4
SENSE
REFERENCE
LEAD