AD775 Analog Devices, AD775 Datasheet - Page 7

• Manufacturer Part Number: AD775
• Description: 8-Bit 20 MSPS/ 60 mW Sampling A/D Converter
• Manufacturer: Analog Devices

REV. 0
In the topology shown in Figure 8, the top of the ladder (V
is shorted to the top bias resistor (V
16), while the bottom of the ladder (V
tom bias resistor (V
a resistive path (nominally 725 ohms) between AV
For nominal supply voltages (5 V and 0 V respectively), this
creates an input range of 0.64 V to 2.73 V.
Both top and bottom of the reference ladder should be de-
coupled, preferably with a chip capacitor to ground to minimize
reference noise.
The topology shown in Figure 9 provides a ground-inclusive
input range. The bottom of the ladder (V
(0 V), while the top of the ladder (V
board bias resistor (V
of 0 V to +2.4 V for AV
floating, or shorted to AV
More elaborate topologies can be used for those wishing to
provide an input span based on an external reference voltage.
The circuit in Figure 10 uses the AD780 2.5 V reference to
drive the top of the ladder (V
ladder grounded to provide an input span of 0 V to +2.5 V. This is
modified in Figure 11 to shift the 2.5 V span up 700 mV.
The AD775 can accommodate dynamic changes in the reference
voltage for gain or offset adjustment. However, conversions that
are in progress, including those in the converter pipeline, while
the reference voltages are changing will be invalid.
0.1 F
Figure 9. Reference Configuration: 0 V to +2.4 V
Figure 10. Reference Configuration: 0 V to 2.5 V
+5V
NC
NC
0.1 F
AV
1
2
3
4
SS
RBS
AD780
RTS
) (Pin 23 shorted to Pin 22). This creates
DD
). This provides a nominal input range
NC = NO CONNECT
SS
16
17
23
22
of 5 V. The V
.
8
7
6
5
RT
), with the bottom (V
325
300
90
AV
AV
NC
NC
NC
DD
SS
RTS
RT
RB
*VALUES FOR
) is connected to the on-
) (Pin 17 shorted to Pin
RESISTANCE
ARE TYPICAL
0.1 F
) is shorted to the bot-
NC
NC
RBS
RB
AD775
) is shorted to AV
pin may be left
16
17
22
23
DD
AD775
RB
and AV
) of the
RT
)
SS
SS
.
.
–7–
ANALOG INPUT
The impedance looking into the analog input is essentially
capacitive, as shown in the equivalent circuit of Figure 12, typi-
cally totalling around 11 pF. A portion of this capacitance is
parasitic; the remainder is part of the switched capacitor struc-
ture of the comparator arrays. The switches close on the rising
edge of the clock, acquire the input voltage, and open on the
clock’s falling edge (the sampling instant). The charge that must
be moved onto the capacitors during acquisition will be a func-
tion of the converter’s previous two samples, but there should be
no sample-to-sample crosstalk so long as ample driving imped-
ance and acquisition time are provided.
For example, to ensure accurate acquisition (to 1/4 bit accuracy)
of a full-scale input step in less than 20 ns, a source impedance
of less than 100 ohms is recommended. Figure 13 shows one
option of input buffer circuitry using the AD817. The AD817
acts as both an inverting buffer and level shifting circuit. In
order to level shift the ground-based input signal to the dc level
required by the input of the AD775, the supply voltage is resis-
tively divided to produce the appropriate voltage at the nonin-
verting input of the AD817. For most applications, the AD817
provides a low cost, high performance level shifter. The AD811
is recommended for systems which require faster settling times.
+5V
0.1 F
Figure 11. Reference Configuration: 0.7 V to 3.2 V
V
3
IN
Figure 12. Equivalent Analog Input Circuit (V
V
IN
AD680
GND
1
V
OUT
2
AV
AV
422
422
140
0.1 F
SS
DD
C1 + C2 + C3
10k
10k
C1
2
3
6
5
AD822
AD822
11pF
10k
10k
500pF
500pF
1
7
SWITCHES EACH
CLOCK CYCLE
SWITCHES ON ALTERNATE
CLOCK CYCLES
20
20
C2
C3
NC
NC
AD775
0.1 F
0.1 F
AD775
16
17
22
23
V
V
V
V
NC = NO CONNECT
RTS
RT
RBS
RB
IN
AD775
)