AD7816-7818 Analog Devices, AD7816-7818 Datasheet - Page 5

• Manufacturer Part Number: AD7816-7818
• Description: Single- and 4-Channel/ 9 us/ 10-Bit ADCs with On-Chip Temperature Sensor
• Manufacturer: Analog Devices

TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
Specifications subject to change without notice.
REV. A
POWER-UP
1a
1b
2
3
4
5
6
7
8
9
10
11
12
13
14a
14b
15
16
17
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to
90% of +5 V) and timed from a voltage level of +1.6 V.
See Figures 16, 17, 20 and 21.
These figures are measured with the load circuit of Figure 3. They are defined as the time required for D
or 2 V for V
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
3
3
3, 4
3, 4
DD
= 3 V
2
9
27
20
50
0
0
10
10
40
40
0
0
20
20
30
30
150
40
400
A, B Versions
10%, as quoted on the specifications page of this data sheet.
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
ns max
ns min
Units
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns max
ns min
1, 2
s max
s max
s max
(V
otherwise noted)
OUTPUT
DD
PIN
= +2.7 V to +5.5 V, GND = 0 V, REF
TO
Test Conditions/Comments
Power-Up Time from Rising Edge of CONVST
Conversion Time Channels 1 to 4
Conversion Time Temperature Sensor
CONVST Pulsewidth
CONVST Falling Edge to BUSY Rising Edge
CS Falling Edge to RD/WR Falling Edge Setup Time
RD/WR Falling Edge to SCLK Falling Edge Setup
D
D
SCLK Low Pulsewidth
SCLK High Pulsewidth
CS Falling Edge to RD/WR Rising Edge Setup Time
RD/WR Rising Edge to SCLK Falling Edge Setup Time
D
D
D
D
BUSY Falling Edge to OTI Falling Edge
RD/WR Rising Edge to OTI Rising Edge
SCLK Rising Edge to CONVST Falling Edge (Acquisition Time of T/H)
50pF
IN
IN
OUT
OUT
OUT
OUT
C
L
Setup Time before SCLK Rising Edge
Hold Time after SCLK Rising Edge
Access Time after RD/WR Rising Edge
Access Time after SCLK Falling Edge
Bus Relinquish Time after Falling Edge of RD/WR
Bus Relinquish Time after Rising Edge of CS
200 A
200 A
–5–
I
I
OL
OL
IN
1.6V
OUT
= +2.5 V. All specifications T
to cross 0.8 V or 2.4 V for V
AD7816/AD7817/AD7818
DD
MIN
= 5 V
to T
MAX
10% and 0.4 V
unless