AD7874 Analog Devices, AD7874 Datasheet - Page 3

• Manufacturer Part Number: AD7874
• Description: LC2MOS 4-Channel/ 12-Bit Simultaneous Sampling Data Acquisition System
• Manufacturer: Analog Devices

REV. C
TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
V
V
V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to V
Operating Temperature Range
Storage Temperature Range . . . . . . . . . . . . –65 C to +150 C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300 C
Power Dissipation (Any Package) to +75 C . . . . . . 1,000 mW
Derates above +75 C by . . . . . . . . . . . . . . . . . . . . 10 mW/ C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7874 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25 C to ensure compliance. All input signals are specified with
t
t
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1
2
3
4
5
6
7
8
CONV
CLK
tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and as such is independent of external bus loading capacitances.
6
7
2
3
DD
DD
SS
IN
A
Commercial (A, B Versions) . . . . . . . . . . . –40 C to +85 C
Extended (S Version) . . . . . . . . . . . . . . . . –55 C to +125 C
is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
= +25 C unless otherwise noted)
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
A, B Versions
50
0
60
0
60
57
5
45
130
31
32.5
31
35
10
1
(V
otherwise noted.)
DD
= +5 V
DD
DD
DD
S Version
50
0
70
0
60
70
5
50
150
31
32.5
31
35
10
+ 0.3 V
+ 0.3 V
+ 0.3 V
5%, V
DD
SS
= –5 V
–3–
5%, AGND = DGND = O V, t
Figure 2. Load Circuit for Bus Relinquish Time
Units
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
s min
s max
s min
s max
s max
Figure 1. Load Circuit for Access Time
7
, quoted in the timing characteristics is the true bus relinquish
TO OUTPUT
TO OUTPUT
PIN
PIN
50pF
50pF
Conditions/Comments
CONVST Pulse Width
CS to RD Setup Time
RD Pulse Width
CS to RD Hold Time
RD to INT Delay
Data Access Time after RD
Bus Relinquish Time after RD
Delay Time between Reads
CONVST to INT, External Clock
CONVST to INT, External Clock
CONVST to INT, Internal Clock
CONVST to INT, Internal Clock
Minimum Input Clock Period
CLK
= 2.5 MHz external unless
1.6mA
200 A
WARNING!
1.6mA
200 A
ESD SENSITIVE DEVICE
+
+
AD7874
2.1V
2.1V