CY7C1399B Cypress Semiconductor, CY7C1399B Datasheet

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CY7C1399B

Manufacturer Part Number
CY7C1399B
Description
32K x 8 3.3V Static RAM
Manufacturer
Cypress Semiconductor
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-05071 Rev. *C
Features
Functional Description
The CY7C1399B is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory ex-
pansion is provided by an active LOW Chip Enable (CE) and
Selection Guide
Note:
1.
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current ( A)
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
• Low active power
• Low-power alpha immune 6T cell
• Plastic SOJ and TSOP packaging
Logic Block Diagram
— 10/12/15 ns
— 216 mW (max.)
For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
CE
WE
OE
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
[1]
INPUT BUFFER
DECODER
32K x 8
ARRAY
COLUMN
3901 North First Street
POWER
DOWN
L
1399B-10
500
10
60
50
active LOW Output Enable (OE) and three-state drivers. The
device has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs are
both LOW, data on the eight data input/output pins (I/O
through I/O
the address present on the address pins (A
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399B is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
7
San Jose
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
) is written into the memory location addressed by
32K x 8 3.3V Static RAM
1399B-12
0
1
2
3
4
5
6
7
500
12
55
50
CA 95134
Pin Configurations
1399B-15
GND
I/O
I/O
I/O
A
A
A
A
A
A
A
A
A
A
10
11
12
13
14
5
6
7
8
9
0
1
2
500
15
50
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
Revised June 19, 2001
SOJ
CY7C1399B
28
27
26
25
24
23
22
21
20
19
18
17
16
15
0
408-943-2600
I/O
V
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
through A
1399B-20
CC
4
3
2
1
0
7
6
5
4
3
500
20
45
50
14
).
0

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CY7C1399B Summary of contents

Page 1

... The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. The CY7C1399B is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I packages. I/O I/O ...

Page 2

... OUT 1/t MAX RC Max MAX Max – 0.3V [4] V – 0.3V 0.3V – 0. 0.3V MAX CY7C1399B I GND ...

Page 3

... MAX Max –0.3V [4] V – 0.3V 0.3V –0. 0.3V, CC f=f MAX Description Test Conditions MHz 351 1.73V CY7C1399B 1399B-15 1399B-20 Min. Max. Min. Max. 2.4 2.4 0.4 0.4 2 +0.3V +0.3V –0.3 0.8 –0.3 0.8 –1 +1 –1 +1 –5 +5 –5 +5 –300 – ...

Page 4

... The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t Document #: 38-05071 Rev. *C [6] Description [7] [7, 8] [7] [7, 8] [9] [7] is less than less than t HZCE LZCE HZOE LZOE and t HZWE CY7C1399B 1399B-10 1399B-12 Min. Max. Min. Max ...

Page 5

... Description [7] [7, 8] [7] [7, 8] [9] [7] (Over the Operating Range - L version only) Description Conditions Com’ 2.0V > V – 0.3V > V – 0. < 0.3V IN CY7C1399B 1399B-15 1399B-20 Min. Max. Min. Max ...

Page 6

... WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05071 Rev. *C DATA RETENTION MODE 3. CDR OHA ACE t DOE t LZOE 50 CY7C1399B 3. DATA VALID t HZOE t HZCE IMPEDANCE DATA VALID t PD 50% HIGH ICC ISB Page ...

Page 7

... During this period, the I/Os are in the output state and input signals should not be applied. Document #: 38-05071 Rev PWE t SD DATA SCE DATA [10, 15 DATA HZWE CY7C1399B VALID VALID VALID IN t LZWE Page ...

Page 8

... CY7C1399B-10ZC CY7C1399BL-10VC CY7C1399BL-10ZC 12 CY7C1399B-12VC CY7C1399B-12ZC CY7C1399BL-12VC CY7C1399BL-12ZC CY7C1399B-12VI CY7C1399B-12ZI 15 CY7C1399B-15VC CY7C1399B-15ZC CY7C1399BL-15VC CY7C1399BL-15ZC CY7C1399B-15VI CY7C1399B-15ZI 20 CY7C1399B-20VC CY7C1399B-20ZC CY7C1399BL-20VC CY7C1399BL-20ZC CY7C1399B-20VI CY7C1399B-20ZI Document #: 38-05071 Rev. *C Mode Deselect/Power-Down Read Write Deselect, Output Disabled Package Name Package Type V21 28-Lead Molded SOJ Z28 28-Lead Thin Small Outline Package ...

Page 9

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Molded SOJ V21 CY7C1399B 51-85031-B 51-85071-*G ...

Page 10

... Document History Page Document Title: CY7C1399B 32K x 8 3.3V Static RAM Document Number: 38-05071 ISSUE REV. ECN NO. DATE ** 107264 05/25/01 *A 107533 06/28/01 *B 116472 09/17/02 *C 224340 See ECN Document #: 38-05071 Rev. *C ORIG. OF CHANGE DESCRIPTION OF CHANGE SZV Change from Spec #: 38-01102 to 38-05071 MAX Add Low Power CEA Add applications foot note to data sheet, page 1 ...

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