MAX3140 Maxim, MAX3140 Datasheet - Page 16

• Manufacturer Part Number: MAX3140
• Description: SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
• Manufacturer: Maxim

SCLK’s rising edge. DOUT (MISO) is read into the µP
on SCLK’s rising edge. The first bit (bit 15) of DOUT
transitions on CS’s falling edge, and bits 14–0 transition
on SCLK’s falling edge. Figure 12 shows the detailed
serial timing specifications for the synchronous SPI
port.
Only 16-bit words are expected. If CS goes high in the
middle of a transmission (any time before the 16th bit),
the sequence is aborted (i.e., data does not get written
to individual registers). Most operations, such as the
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
Figure 12. Detailed Serial Timing Specifications for the Synchronous Port
Figure 13. SPI Interface (Write Configuration)
Figure 14. Parity and Word Length Control
16
DOUT
SCLK
DIN
CS
______________________________________________________________________________________
DOUT
SCLK
DIN
CS
1
R
1
t
CSO
1
T
TIME
IDLE
IDLE
IDLE
IDLE
2
FEN
t
DV
0
t
CSS
3
t
DS
START
START
START
START
SHDN
t
DH
0
4
PE = 0, L = 0
PE = 0, L = 1
PE = 1, L = 0
PE = 1, L = 1
D0
D0
D0
D0
TM
0
5
D1
D1
D1
D1
RM
t
0
CL
6
D2
D2
D2
D2
PM
0
7
t
CH
D3
D3
D3
D3
RAM
0
8
D4
D4
D4
D4
IR
0
9
clearing of internal registers, are executed only on CS’s
rising edge. Every time CS goes low, a new 16-bit
stream is expected. Figure 13 shows an example of
using the WRITE CONFIGURATION register.
Table 1 describes the bits located in the WRITE CON-
FIGURATION, READ CONFIGURATION, WRITE DATA,
and READ DATA registers. This table also describes
whether the bit is a read or write bit and what the
power-on reset states (POR) of the bits are. Figure 14
shows an example of parity and word length control.
D5
D5
D5
D5
ST
0
10
D6
D6
D6
D6
PE
0
11
STOP
SECOND STOP BIT IS OMITTED IF ST = 0.
D7
D7
Pt
0
L
12
t
STOP
DO
STOP
STOP
Pt
B3
0
13
STOP
STOP
STOP
IDLE
B2
0
14
STOP
IDLE
IDLE
B1
t
0
CSH
15
IDLE
B0
0
UPDATED
16
DATA
t
TR
t
CS1