MM74HC02 Fairchild, MM74HC02 Datasheet

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MM74HC02

Manufacturer Part Number
MM74HC02
Description
Quad 2-Input NOR Gate
Manufacturer
Fairchild
Datasheet

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© 1999 Fairchild Semiconductor Corporation
MM74HC02M
MM74HC02SJ
MM74HC02MTC
MM74HC02N
MM74HC02
Quad 2-Input NOR Gate
General Description
The MM74HC02 NOR gates utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low power consumption of standard
CMOS integrated circuits. All gates have buffered outputs,
providing high noise immunity and the ability to drive 10
LS-TTL loads. The 74HC logic family is functionally as well
as pin-out compatible with the standard 74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.)
Connection Diagram
Logic Diagram
Order Number
Package Number
MTC14
M14A
M14D
N14A
Pin Assignment for DIP, SOIC, SOP and TSSOP
CC
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
and ground.
DS005294.prf
Top View
Features
Typical propagation delay: 8 ns
Wide power supply range: 2–6V
Low quiescent supply current: 20
(74HC Series)
Low input current: 1 A maximum
High output current: 4 mA minimum
Package Description
September 1983
Revised February 1999
www.fairchildsemi.com
A maximum

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MM74HC02 Summary of contents

Page 1

... MM74HC02 Quad 2-Input NOR Gate General Description The MM74HC02 NOR gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs, providing high noise immunity and the ability to drive 10 LS-TTL loads ...

Page 2

... Note 4: For a power supply of 5V 10% the worst case output voltages (V designing with this supply. Worst case V and V occur and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used www.fairchildsemi.com Recommended Operating (Note 1) Conditions 0.5 to 7.0V 1 1.5V Supply Voltage ( 0 0.5V ...

Page 3

... Guaranteed Limits 2. 113 and the no load dynamic current consumption Guaranteed Units Limit 125 C A Units 134 110 www.fairchildsemi.com ...

Page 4

... Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M14A Package Number M14D 4 ...

Page 5

... Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 5 www.fairchildsemi.com ...

Page 6

... Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. Package Number N14A 2 ...

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