MM74HCT540 Fairchild, MM74HCT540 Datasheet

no-image

MM74HCT540

Manufacturer Part Number
MM74HCT540
Description
Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer
Manufacturer
Fairchild
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MM74HCT540WM
Manufacturer:
Fairchild Semiconductor
Quantity:
1 782
© 1999 Fairchild Semiconductor Corporation
MM74HCT540WM
MM74HCT540SJ
MM74HCT540MTC
MM74HCT540N
MM74HCT541WM
MM74HCT541SJ
MM74HCT541MTC
MM74HCT541N
MM74HCT540 • MM74HCT541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HCT540 and MM74HCT541 3-STATE buffers
utilize advanced silicon-gate CMOS technology and are
general purpose high speed inverting and non-inverting
buffers. They possess high drive current outputs which
enable high speed operation even when driving large bus
capacitances. These circuits achieve speeds comparable
to low power Schottky devices, while retaining the low
power consumption of CMOS. Both devices are TTL input
compatible and have a fanout of 15 LS-TTL equivalent
inputs.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Order Number
Package Number
MM74HCT540
Top View
MTC20
MTC20
M20B
M20D
M20B
M20D
N20A
N20A
Pin Assignments for DIP, SOIC, SOP and TSSOP
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DS006040.prf
The MM74HCT540 is an inverting buffer and the
MM74HCT541 is a non-inverting buffer. The 3-STATE con-
trol gate operates as a two-input NOR such that if either G1
or G2 are HIGH, all eight outputs are in the high-imped-
ance state.
In order to enhance PC board layout, the MM74HCT540
and MM74HCT541 offers a pinout having inputs and out-
puts on opposite sides of the package. All inputs are pro-
tected from damage due to static discharge by diodes to
V
Features
CC
TTL input compatible
Typical propagation delay: 12 ns
3-STATE outputs for connection to system buses
Low quiescent current: 80 A
Output current: 6 mA (min.)
and ground.
Package Description
MM74HCT541
Top View
February 1984
Revised February 1999
www.fairchildsemi.com

Related parts for MM74HCT540

MM74HCT540 Summary of contents

Page 1

... NOR such that if either are HIGH, all eight outputs are in the high-imped- ance state. In order to enhance PC board layout, the MM74HCT540 and MM74HCT541 offers a pinout having inputs and out- puts on opposite sides of the package. All inputs are pro- ...

Page 2

... Output Leakage Current I Maximum Quiescent Supply Current OUT V 2.4V or 0.5V (Note 4) IN Note 4: Measured per input. All other inputs GND. CC www.fairchildsemi.com Recommended Operating (Note 1) Conditions 0.5 to 7.0V 1 1.5V Supply Voltage ( 0 0.5V DC Input or Output Voltage OUT ...

Page 3

... Maximum Output PHL PLH Propagation Delay Maximum Output PZL PZH Enable Time Maximum Output PLZ PHZ Disable Time AC Electrical Characteristics MM74HCT540: V 5.0V 10 (unless otherwise specified Symbol Parameter Maximum Output PHL PLH L Propagation Delay ...

Page 4

... Capacitance C Maximum Output OUT Capacitance C Power Dissipation (per output) PD Capacitance (Note 6) Note 6: C determines the no load dynamic power consumption www.fairchildsemi.com Conditions Typ Conditions ...

Page 5

... Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20B Package Number M20D 5 www.fairchildsemi.com ...

Page 6

... Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC20 6 ...

Page 7

... Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. Package Number N20A 2 ...

Related keywords