MM74HCT574 Fairchild, MM74HCT574 Datasheet

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MM74HCT574

Manufacturer Part Number
MM74HCT574
Description
Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
Manufacturer
Fairchild
Datasheet

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© 1999 Fairchild Semiconductor Corporation
MM74HCT573WM
MM74HCT573SJ
MM74HCT573MTC
MM74HCT573N
MM74HCT574WM
MM74HCT574SJ
MM74HCT574MTC
MM74HCT574N
MM74HCT573 • MM74HCT574
Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
General Description
The
MM74HCT574 octal D-type flip-flop advanced silicon-gate
CMOS technology, which provides the inherent benefits of
low power consumption and wide power supply range, but
are LS-TTL input and output characteristic and pin-out
compatible. The 3-STATE outputs are capable of driving 15
LS-TTL loads. All inputs are protected from damage due to
static discharge by internal diodes to V
When the MM74HCT573 Latch Enable input is HIGH, the
Q outputs will follow the D inputs. When the Latch Enable
goes LOW, data at the D inputs will be retained at the out-
puts until Latch Enable returns HIGH again. When a high
logic level is applied to the Output Control input, all outputs
go to a high impedance state, regardless of what signals
are present at the other inputs and the state of the storage
elements.
The MM74HCT574 are positive edge triggered flip-flops.
Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on positive
Ordering Codes:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Order Number
MM74HCT573
Package Number
octal
MTC20
MTC20
M20B
M20D
M20B
M20D
N20A
N20A
D-type
CC
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
and ground.
DS010627.prf
latches
and
going transitions of the Clock (CK) input. When a high logic
level is applied to the Output Control (OC) input, all outputs
go to a high impedance state, regardless of what signals
are present at the other inputs and the state of the storage
elements.
The MM74HCT devices are intended to interface between
TTL and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
TTL input characteristic compatible
Typical propagation delay: 18 ns
Low input current: 1 A maximum
Low quiescent current: 80 A maximum
Compatible with bus-oriented systems
Output drive capability: 15 LS-TTL loads
Package Description
February 1990
Revised May 1999
www.fairchildsemi.com

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MM74HCT574 Summary of contents

Page 1

... The MM74HCT574 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive Ordering Codes: ...

Page 2

... HIGH Level L LOW Level Q Level of output before steady-state input conditions were established High Impedance State MM74HCT574 Output LE Data Control HIGH Level L LOW Level Q Level of output before steady-state input conditions were established. ...

Page 3

... 6.0 mA, V 4.5V 4.2 3.98 CC 7.2 mA, V 5.5V 5.7 4. 0.1 6.0 mA, V 4.5V 0.2 0.26 CC 7.2 mA, V 5.5V 0.2 0. GND, 0 GND 0 GND 8.0 1.5 3 Min Max Units 4.5 5 500 125 C A Units 2.0 2.0 V 0.8 0.8 V 0 3.84 3.7 4.84 4.7 0.1 0.1 V 0.33 0.4 0.33 0.4 1.0 1 160 A 1.8 2.0 mA www.fairchildsemi.com ...

Page 4

... C Maximum Input Capacitance IN C Maximum Output Capacitance OUT C Power Dissipation Capacitance PD (Note 5) Note 5: C determines the no load dynamic power consumption www.fairchildsemi.com MM74HCT573 Conditions Typ ...

Page 5

... Note 6: C determines the no load power consumption MM74HCT574 Conditions Typ MM74HCT574 Conditions Typ ...

Page 6

... Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20B Package Number M20D 6 ...

Page 7

... Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com ...

Page 8

... Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. Package Number N20A 2 ...

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