74HCT74 Philips, 74HCT74 Datasheet - Page 2

• Manufacturer Part Number: 74HCT74
• Description: Dual D-type flip-flop with set and reset; positive-edge trigger
• Manufacturer: Philips

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT74 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT74 are dual positive-edge triggered, D-type
flip-flops with individual data (D) inputs, clock (CP) inputs,
set (S
Q outputs.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
1998 Feb 23
t
f
C
C
PHL
max
SYMBOL
Output capability: standard
I
I
PD
Dual D-type flip-flop with set and reset;
positive-edge trigger
CC
f
f
C
V
For HCT the condition is V
i
o
/ t
CC
PD
= input frequency in MHz
L
D
category: flip-flops
= output frequency in MHz
(C
PLH
) and reset (R
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
propagation delay
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
2
nCP to nQ, nQ
nS
nR
= 25 C; t
V
D
f
D
o
D
CC
) = sum of outputs
to nQ, nQ
to nQ, nQ
) inputs; also complementary Q and
2
f
r
i
= t
I
PARAMETER
= GND to V
I
f
= GND to V
= 6 ns
(C
L
V
CC
CC
2
CC
f
o
) where:
1.5 V
2
C
notes 1 and 2
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
L
D
= 15 pF; V
in W):
CONDITIONS
CC
= 5 V
14
15
16
76
3.5
24
HC
TYPICAL
Product specification
74HC/HCT74
15
18
18
59
3.5
29
HCT
ns
ns
ns
MHz
pF
pF
UNIT