74VHC125 Fairchild Semiconductor, 74VHC125 Datasheet

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74VHC125

Manufacturer Part Number
74VHC125
Description
Quad Buffer with 3-STATE Outputs
Manufacturer
Fairchild Semiconductor
Datasheet

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DESCRIPTION
The 74VHC125 is an advanced high-speed
CMOS QUAD BUS BUFFERS fabricated with
sub-micron silicon gate and double-layer metal
wiring C
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
HIGH SPEED: t
LOW POWER DISSIPATION:
I
HIGH NOISE IMMUNITY:
V
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
CC
PLH
OH
NIH
CC
= 4 A (MAX.) at T
| = I
(OPR) = 2V to 5.5V
= V
2
t
MOS technology.
PHL
OL
NIL
= 8 mA (MIN)
= 28% V
OLP
PD
= 3.8 ns (TYP.) at V
= 0.8V (Max.)
CC
A
(MIN.)
= 25
o
C
CC
= 5V
QUAD BUS BUFFERS (3-STATE)
This device requires the 3-STATE control input G
to be set high to place the output into the high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2kV ESD immunity and transient excess
voltage.
(Micro Package)
74VHC125M
M
ORDER CODES :
74VHC125
(TSSOP Package)
74VHC125T
PRELIMINARY DATA
T
1/8

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74VHC125 Summary of contents

Page 1

... PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 125 IMPROVED LATCH-UP IMMUNITY LOW NOISE 0.8V (Max.) OLP DESCRIPTION The 74VHC125 is an advanced high-speed CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal 2 wiring C MOS technology. PIN CONNECTION AND IEC LOGIC SYMBOLS ...

Page 2

... INPUT EQUIVALENT CIRCUIT ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current Ground Current CC GND CC T Storage Temperature stg T Lead Temperature (10 sec) L Absolute Maximum Ratings are those values beyond which damage to the device may occur ...

Page 3

... (pF ) Min. Typ . (*) 15 5.6 (*) 50 8.1 (**) 15 3.8 (**) 50 5.3 (*) 5.4 L (*) 7.9 L (**) 3.6 L (**) 5.1 L (*) 9.5 L (**) 6.1 L 74VHC125 Value - Max. Min . Max. 1.5 V 0.7V CC 0.5 0.5 V 0.3V 0. 1.9 2.9 V 4.4 2.48 3.8 0.1 0.1 0.1 0.1 V 0.1 0.1 0.36 0.44 0.36 0.44 0.25 2.5 A 0.1 1 Value - Max. Min . ...

Page 4

... CAPACITIVE CHARACTERISTICS Symb ol Parameter C Input Capacitance IN C Output Capacitance OUT C Power Dissipation PD Capacitance (note isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto PD Test Circuit).Average operting current can be obtained by the following equation. I ...

Page 5

... WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 74VHC125 5/8 ...

Page 6

... SO-14 MECHANICAL DATA DIM. MIN. TYP 0 0. 8.55 E 5.8 e 1.27 e3 7.62 F 3.8 G 4 6/8 mm MAX. MIN. 1.75 0.2 0.003 1.65 0.46 0.013 0.25 0.007 0.5 45 (typ.) 8.75 0.336 6.2 0.228 4.0 0.149 5.3 0.181 1.27 0.019 0.68 8 (max.) inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 0.019 0.344 0.244 0.050 0.300 0.157 0.208 ...

Page 7

... PIN 1 IDENTIFICATION 1 MAX. MIN. 1.1 0.15 0.002 0.95 0.335 0.30 0.0075 0.20 0.0035 5.1 0.193 6.5 0.246 4.48 0.169 0.70 0.020 74VHC125 inch TYP. MAX. 0.433 0.004 0.006 0.354 0.374 0.0118 0.0079 0.197 0.201 0.252 0.256 0.173 0.176 0.0256 BSC 0.024 0.028 L E 7/8 ...

Page 8

... Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice ...

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