74LV164 Philips, 74LV164 Datasheet - Page 2

• Manufacturer Part Number: 74LV164
• Description: 8-bit serial-in/parallel-out shift register
• Manufacturer: Philips

1. C
2. The condition is V
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
t
f
C
C
14-Pin Plastic DIL
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
1998 May 07
PHL
max
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
Typical V
T
Typical V
T
Gated serial data inputs
Asynchronous master reset
Output capability: standard
I
8-bit serial-in/parallel-out shift register
I
PD
CC
P
f
f
S (C
amb
amb
i
o
PD
D
= input frequency in MHz; C
SYMBOL
/t
= output frequency in MHz; V
category: MSI
PLH
= C
= 25 C
= 25 C
L
is used to determine the dynamic power dissipation (P
PD
OLP
OHV
V
amb
PACKAGES
CC
(output ground bounce) t 0.8V @ V
(output V
V
2
= 25 C; t
CC
2
f
I
Propagation delay
CP to Q
MR to Q
Maximum clock frequency
Input capacitance
Power dissipation capacitance per gate
o
x f
= GND to V
) = sum of the outputs.
i
OH
r
)S (C
=t
undershoot) u 2V @ V
f
n
v2.5 ns
n
L
L
CC
= output load capacitance in pF;
CC
PARAMETER
V
CC
= supply voltage in V;
CC
TEMPERATURE RANGE
2
= 2.7V and V
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
f
o
) where:
CC
CC
CC
= 3.3V,
= 3.3V,
= 3.6V
D
in W)
C
V
V
Notes 1 and 2
OUTSIDE NORTH AMERICA
CC
CC
L
= 15pF
2
= 3.3V
= 3.3V
DESCRIPTION
The 74LV164 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT164.
The 74LV164 is an 8-bit edge-triggered shift register with serial data
entry and an output from each of the eight stages. Data is entered
serially through one of two inputs (D
used as an active HIGH enable for data entry through the other
input. Both inputs must be connected together or an unused input
must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of
the clock (CP) input and enters into Q
the two data inputs (D
the rising clock edge.
A LOW on the master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all outputs LOW.
74LV164 PW
74LV164 DB
CONDITIONS
74LV164 N
74LV164 D
sa
, D
NORTH AMERICA
sb
74LV164PW DH
) that existed one set-up time prior to
74LV164 DB
74LV164 N
74LV164 D
TYPICAL
sa
3.5
0
12
12
78
40
or D
, which is the logical AND of
sb
); either input can be
Product specification
74LV164
853–1961 19349
PKG. DWG. #
SOT108-1
SOT337-1
SOT402-1
SOT27-1
UNIT
MHz
ns
pF
pF