74LVC109 Philips, 74LVC109 Datasheet - Page 2

• Manufacturer Part Number: 74LVC109
• Description: Dual JK flip-flop with set and reset; positive-edge trigger
• Manufacturer: Philips

1. C
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
NOTE:
ORDERING INFORMATION
PIN CONFIGURATION
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
1998 Apr 28
Wide supply voltage range of 1.2 to 3.6 V
In accordance with JEDEC standard no. 8-1A.
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output capability: standard
I
Dual JK flip-flop with set and reset; positive-edge trigger
CC
P
f
f
i
o
SYMBOL
t
PD
D
PHL
= input frequency in MHz; C
(C
= output frequency in MHz; V
category: flip-flops
= C
f
C
max
L
C
is used to determine the dynamic power dissipation (P
PD
/t
I
PLH
PD
V
PACKAGES
CC
amb
2
V
CC
= 25 C; t
f
GND
Propagation delay
nCP to nQ, nQ
nS
nR
Maximum clock frequency
Input capacitance
Power dissipation capacitance per flip-flop
o
1R
1S D
2
1CP
) = sum of the outputs.
1Q
1Q
1K
1J
D
D
D
f
i
to nQ, nQ
to nQ, nQ
) (C
1
2
3
4
5
6
7
8
r
= t
f
L
2.5 ns
L
PARAMETER
= output load capacity in pF;
CC
V
CC
= supply voltage in V;
2
TEMPERATURE RANGE
SV00517
16
15
14
13
12
11
10
9
f
o
) where:
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
V
2R
2J
2K
2CP
2S
2Q
2Q
CC
D
D
D
C
V
V
in W)
CC
I
L
= GND to V
= 50 pF;
OUTSIDE NORTH AMERICA
= 3.3 V
2
CONDITIONS
DESCRIPTION
The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT109.
The 74LVC109 is a dual positive-edge triggered JK-type flip-flop
featuring individual J, K inputs, clock (CP) inputs, set (S
(R
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input.
The J and K inputs control the state changes of the flip-flops as
described in the mode select function table. The J and K inputs must
be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation. The JK design allows operation as a
D-type flip-flop by tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
PIN DESCRIPTION
74LVC109 DB
74LVC109 PW
1, 15
2, 14, 3, 13
4, 12
5, 11
6, 10
7, 9
8
16
74LVC109 D
NUMBER
D
CC
) inputs; also complementary Q and Q outputs.
PIN
1
1R
1J, 2J, 1K, 2K
1CP, 2CP
1S
1Q, 2Q
1Q, 2Q
GND
V
CC
SYMBOL
D
D,
, 2R
2S
D
D
NORTH AMERICA
74LVC109PW DH
74LVC109 DB
74LVC109 D
Asynchronous reset input
(active LOW)
Synchronous inputs;
flip-flops 1 and 2
Clock input
(LOW-to-HIGH, edge-triggered)
Asynchronous set inputs
(active LOW)
True flip-flop outputs
Complement flip-flop outputs
Ground (O V)
Positive supply voltage
TYPICAL
250
4.0
4.5
4.5
5.0
27
FUNCTION
Product specification
74LVC109
853–1947 19308
PKG. DWG. #
SOT109-1
SOT338-1
SOT403-1
D
) and reset
UNIT
MHz
ns
pF
pF