74LVC16373 Philips, 74LVC16373 Datasheet - Page 2

• Manufacturer Part Number: 74LVC16373
• Description: 16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs 3-State
• Manufacturer: Philips

1. C
Philips Semiconductors
FEATURES
DESCRIPTION
The 74LVC(H)16373A is a 16-bit D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for bus
oriented applications. One latch enable (LE) input and one output
enable (OE) are provided for each octal. Inputs can be driven from
either 3.3V or 5V devices. In 3-State operation, outputs can handle
5V. These features allow the use of these devices in a mixed
3.3V/5V environment.
The 74LVC(H)16373A consists of 2 sections of eight D-type
transparent latches with 3-State true outputs. When LE is HIGH,
data at the Dn inputs enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The 74LVCH16373A bus hold data inputs eliminates the need for
external pull up resistors to hold unused inputs.
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
1998 Mar 17
5 volt tolerant inputs/outputs for interfacing with 5V logic
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
Low inductance multiple power and ground pins for minimum
noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH167373A only)
High impedance when V
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
t
C
C
PHL
P
f
f
S (C
SYMBOL
i
o
I
PD
PD
D
= input frequency in MHz; C
= output frequency in MHz; V
= C
/t
L
PLH
is used to determine the dynamic power dissipation (P
PD
V
amb
PACKAGES
CC
TM
V
2
= 25 C; t
CC
flow-through standard pin-out architecture
Propagation delay
Dn to Qn
LE to Qn
Input capacitance
Power dissipation capacitance per latch
f
2
o
) = sum of outputs.
f
i
+ S (C
r
CC
= t
f
= 0
L
2.5ns
L
PARAMETER
V
= output load capacity in pF;
CC
CC
= supply voltage in V;
2
TEMPERATURE RANGE
f
o
) where:
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
D
in W):
C
V
V
CC
CC
L
OUTSIDE NORTH AMERICA
= 50pF
= 3.3V
= 3.3V
2
74LVCH16373A DGG
74LVC16373A DGG
74LVCH16373A DL
74LVC16373A DL
PIN CONFIGURATION
CONDITIONS
GND
GND
GND
GND
1OE
1Q4
1Q5
2Q3
2Q4
2Q6
2Q7
2OE
1Q0
1Q1
1Q2
1Q3
V
1Q6
1Q7
2Q0
2Q1
2Q2
V
2Q5
CC
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
NORTH AMERICA
VCH16373A DGG
VC16373A DGG
VCH16373A DL
VC16373A DL
SW00066
74LVCH16373A
74LVC16373A/
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TYPICAL
1LE
1D0
1D1
GND
1D2
1D3
V
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
V
2D4
2D5
GND
2D6
2D7
2LE
Product specification
CC
CC
3.0
3.4
5.0
26
DWG NUMBER
853-2027 19112
SOT370-1
SOT362-1
SOT370-1
SOT362-1
UNIT
pF
pF
ns