AD8345-EVAL Analog Devices, AD8345-EVAL Datasheet
AD8345-EVAL
Related parts for AD8345-EVAL
AD8345-EVAL Summary of contents
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... BIAS ENBL 8 APPLICATIONS The AD8345 Modulator can be used as the IF transmit modu- lator in digital communication systems such as GSM and PCS transceivers. It can also directly modulate an LO signal to produce QPSK and various QAM formats for 900 MHz com- munication systems as well as digital TV and CATV systems. ...
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... AD8345–SPECIFICATIONS 0 each side for a 1.2 V p-p differential input, I and Q inputs driven in quadrature @ 1 MHz Baseband Frequency unless otherwise noted.) A Parameters Conditions RF OUTPUT 1 Operating Frequency Output Power Output P1 dB Noise Floor 20 MHz Offset from LO, All BB Inputs at 0.7 V Quadrature Error (CDMA IS95 Setup, Refer to Figure 13) ...
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... AD8345 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Model Temperature Range AD8345ARE –40°C to +85°C AD8345ARE-REEL AD8345ARE-REEL7 AD8345-EVAL PIN CONFIGURATION IBBP 1 IBBN 2 COM3 3 4 ...
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... AD8345 Pin No. Mnemonic Function 1, 2 IBBP, IBBN I Channel Baseband Differential Input Pins. These high impedance inputs should be dc biased to approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin (0 V). This gives a differential drive of 1.2 V p-p. Inputs are not self-biasing so external biasing circuitry must be used in ac-coupled applications. ...
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... V = 2.7V, DIFFERENTIAL INPUT = 200mV p-p S –45 –46 –47 –48 –49 – 250 300 350 ° AD8345 T = – 400 450 500 550 600 650 700 750 800 850 900 950 1000 LO FREQUENCY – MHz ...
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... AD8345 –30 –32 –34 –36 – 5V, DIFFERENTIAL INPUT = 1.2V p-p –40 S –42 –44 – 2.7V, DIFFERENTIAL INPUT = 200mV p-p S –48 –50 –40 – TEMPERATURE – + – –86 –82 –78 –74 –70 –66 CARRIER FEEDTHROUGH – dBm AFTER NULLING TO – ...
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... AD8345 = 5V, DIFFERENTIAL INPUT = 1.2V p 2.7V, DIFFERENTIAL INPUT = 200mV p-p S – TEMPERATURE – C 1GHz SMITH CHART NORMALIZED ...
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... LO LEVEL – dBm CIRCUIT DESCRIPTION Overview The AD8345 can be divided into the following sections: Local Oscillator (LO) Interface, Mixer, Differential Voltage-to-Cur- rent (V-to-I) Converter, Differential-to-Single-Ended (D-to-S) Converter, and Bias. A block diagram of the part is shown in Figure 2. LOIP PHASE SPLITTER ...
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... V p-p differential signal with a bias level of 0.7 V; that is, each input should swing from 0 the AD8345 is being run on a lower supply voltage, the peak-to-peak voltage on the I and Q channel inputs must be reduced to avoid input clipping. For example supply volt- age of 2 ...
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... Where only single-ended I and Q signals are available, a differ- ential amplifier such as the AD8132 or AD8138 can be used to generate the required differential drive signal for the AD8345. Even though most DACs have differential outputs, using a single-ended low-pass filter between the dual DAC and the I and Q inputs, may be more desirable from the perspective of component count and cost ...
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... Resistor pads are provided in case termination at the I and Q inputs is required. The local oscillator input (LO) is terminated to approximately 50 Ω with an external 50 Ω resistor to ground. A 1:1 wide-band transformer (ETC1-1-13) provides a differential drive to the AD8345’s differential LO input. The device can also be driven single-ended by shorting out T1. AD8345 VPS1 ...
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... ENBL IP QP COMPONENT SIDE DUT ENBL AD8345 EVAL BOARD R1 AD8345 (OPEN) QBBP 1 IBBP 16 2 IBBN QBBN 15 R2 (OPEN) 3 COM3 COM3 14 4 COM1 COM3 13 C1 1000pF LOIN ...
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... CHARACTERIZATION SETUPS SSB Setup Essentially, two primary setups were used to characterize the AD8345. These setups are shown in Figures 11 and 13. Figure 11 shows the setup used to evaluate the product as a Single Sideband modulator. The interface board converts the single- ended I and Q inputs from the arbitrary function generator to differential inputs with a dc bias of approximately 0 ...
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... CENTER = 880MHz WCDMA 3GPP For evaluating the AD8345 for WCDMA, the 3GPP standard was used with a Chip Rate of 3.84 MHz. The plot in Figure ACPR plot of the AD8345 using “Test Model 1” from the 3GPP specification with 64 channels active. –10 –20 –30 – ...
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... OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead HTSSOP with Exposed Pad (RE-16) 0.201 (5.10) 0.193 (4.90 0.177 (4.50) 0.169 (4.30) 0.118 (3.0) EXPOSED PAD SQ 0.256 (6.50) 0.246 (6.25 PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) SEATING BSC 0.0075 (0.19) PLANE 0.0035 (0.090) AD8345 0.028 (0.70) 0.020 (0.50) ...
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