CY7C185-25ZC Cypress Semiconductor, CY7C185-25ZC Datasheet - Page 6

• Manufacturer Part Number: CY7C185-25ZC
• Description: 8K x 8 Static RAM
• Manufacturer: Cypress Semiconductor

Write Cycle no.2 (CE Controlled)
Switching Waveforms
Write Cycle No.3 (WE Controlled, OE LOW)
Notes:
10. WE is HIGH for read cycle.
12. The internal write time of the memory is defined by the overlap of CE
13. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
14. If CE
15. During this period, the I/Os are in the output state and input signals should not be applied.
11. Data I/O is High Z if OE = V
9.
ADDRESS
ADDRESS
DATA I/O
DATA I/O
Device is continuously selected. OE, CE
to initiate write. A write can be terminated by CE
rising edge of the signal that terminates the write.
CE
CE
WE
CE
CE
WE
1
1
2
goes HIGH or CE
1
2
2
goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
NOTE 15
t
IH
SA
, CE
(continued)
1
= V
[12,13,15]
t
IH
HZWE
1
, WE = V
= V
t
SA
IL
. CE
1
or WE going HIGH or CE
IL
FOR REVIEW ONLY
2
[12,13,14,15]
or CE
= V
IH.
2
=V
t
IL
AW
t
.
t
SCE2
t
SCE1
AW
1
LOW, CE
t
WC
t
WC
6
2
going LOW. The data input set-up and hold timing should be referenced to the
2
HIGH and WE LOW. CE
DATA
DATA
t
t
SCE1
SCE2
t
t
SD
SD
HZWE
IN
IN
VALID
VALID
and t
SD
.
1
and WE must be LOW and CE
t
HD
t
t
HA
LZWE
t
t
HD
HA
CY7C185
2
must be HIGH
C185–10
C185–9