M48T08 ST Microelectronics, M48T08 Datasheet - Page 12

• Manufacturer Part Number: M48T08
• Description: 64 Kbit 8Kb x 8 TIMEKEEPER SRAM
• Manufacturer: ST Microelectronics

M48T08, M48T18
Setting the Clock (cont’d)
Resetting the WRITE bit to a ’0’ then transfers the
values of all time registers (1FF9h-1FFFh) to the
actual TIMEKEEPER counters and allows normal
operation to resume. The FT bit and the bits marked
as ’0’ in Table 11 must be written to ’0’ to allow for
normal TIMEKEEPER and RAM operation.
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" for information on
Century Rollover.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a ’1’ stops the oscillator. The M48T08/18 is shipped
from STMicroelectronics with the STOP bit set to a
’1’. When reset to a ’0’, the M48T08/18 oscillator
starts within 1 second.
Calibrating the Clock
The M48T08/18 is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz. A
typical M48T08/18 is accurate within 1 minute per
month at 25 C without calibration. The devices are
tested not to exceed 35 PPM (parts per million)
oscillator frequency error at 25 C, which equates
to about
The oscillation rate of any crystal changes with
temperature. Figure 11 shows the frequency error
that can be expected at various temperatures. Most
clock chips compensate for crystal frequency and
Figure 10. Clock Calibration
12/19
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
1.53 minutes per month.
temperature shift error with cumbersome trim ca-
pacitors. The M48T08/18 design, however, em-
ploys periodic counter correction. The calibration
circuit adds or subtracts counts from the oscillator
divider circuit at the divide by 256 stage, as shown
in Figure 10. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five bit Calibration byte found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits in the Control register. This byte can be set to
represent any value between 0 and 31 in binary
form. The sixth bit is a sign bit; ’1’ indicates positive
calibration, ’0’ indicates negative calibration. Cali-
bration occurs within a 64 minute cycle. The first 62
minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened
by 256 oscillator cycles. If a binary ’1’ is loaded into
the register, only the first 2 minutes in the 64 minute
cycle will be modified; if a binary 6 is loaded, the
first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles; that is
+4.068 or -2.034 PPM of adjustment per calibration
step in the calibration register. Assuming that the
oscillator is in fact running at exactly 32,768 Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or - 5.35 seconds per month
which corresponds to a total range of +5.5 or - 2.75
minutes per month.
AI00594B