M48T37 ST Microelectronics, M48T37 Datasheet - Page 14

• Manufacturer Part Number: M48T37
• Description: 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM
• Manufacturer: ST Microelectronics

M48T37Y, M48T37V
Figure 12. Back-up Mode Alarm Waveforms
Table 12. Alarm Repeat Mode
WATCHDOG TIMER
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the eight bit Watchdog Register, ad-
dress 7FF7h. The five bits (BMB4-BMB0) store a
binary multiplier and the two lower order bits (RB1-
RB0) select the resolution, where 00 = 1/16 sec-
ond, 01 = 1/4second, 10 = 1 second, and 11 = 4
seconds. The amount of time-out is then deter-
mined to be the multiplication of the five bit multi-
plier value with the resolution. (For example:
writing 00001110 in the Watchdog Register = 3x1
or 3 seconds).
Note: Accuracy of timer is within
resolution.
14/20
RPT4
1
1
1
1
0
V CC
V PFD (max)
V PFD (min)
V SO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
RPT3
1
1
1
0
0
RPT2
1
1
0
0
0
RPT1
1
0
0
0
0
HIGH-Z
Once per Second
Once per Minute
Once per Hour
Once per Day
Once per Month
Alarm Activated
the selected
If the processor does not reset the timer within the
specified period, the M48T37Y/37V sets the
Watchdog Flag (WDF) and generates a watchdog
interrupt or a microprocessor reset. WDF is reset
by reading the Flags Register (Address 1FF0h).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit. When set to a ‘0’, the
watchdog will activate the IRQ/FT pin when timed-
out. When WDS is set to a ‘1’, the watchdog will
output a negative pulse on the RST pin for a dura-
tion of 40ms to 200ms. The Watchdog register and
the FT bit will reset to a ’0’ at the end of a Watch-
dog time-out when the WDS bit is set to a ‘1’.
The watchdog timer resets when the microproces-
sor performs a re-write of the Watchdog Register
or an edge transition, (low to high / high to low) on
the WDI pin occurs. The time-out period then
starts over.
The watchdog timer is disabled by writing a value
of 00000000 to the eight bits in the Watchdog Reg-
ister. Should the watchdog timer time out, a value
of 00h needs to be written to the Watchdog Regis-
ter in order to clear the IRQ/FT pin.
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied. The WDI
pin should be connected to V
tREC
SS
if not used.
HIGH-Z
AI03254B