PCF84C00B Philips Semiconductors, PCF84C00B Datasheet - Page 9
![no-image](/images/manufacturer_photos/0/5/522/philips_semiconductors_sml.jpg)
PCF84C00B
Manufacturer Part Number
PCF84C00B
Description
8-bit microcontroller with I2C-bus interface
Manufacturer
Philips Semiconductors
Datasheet
1.PCF84C00B.pdf
(24 pages)
Philips Semiconductors
6
6.1
The PCF84C00B package has standard pinning on the
bottom to facilitate insertion as a mask-programmed
device. An EPROM can be mounted on top in an additional
socket. The total package height is greater than the height
of a standard DIP package. The PCF84C00B can address
up to 8 kbytes of external ROM/RAM, and has 256 bytes
of internal data RAM.
6.2
The PCF84C00T microcontroller contains no on-chip
ROM, but has all address and data lines brought out to
access an external ROM or EPROM. Consequently, this
version has more pins (see Fig.5) than the devices in the
PCF84CxxxA family with on-chip or ‘piggy-back’ ROM.
The PCF84C00T can address up to 8 kbytes of external
program memory, and has 256 bytes of internal data RAM.
6.3
Data memory consists of 256 bytes of Random-Access
Memory (RAM). All locations are indirectly addressable
using RAM pointer registers; up to 16 designated locations
are directly addressable. Memory also includes an 8-level
program counter stack addressed by a 3-bit stack pointer.
6.4
Each device has 23 I/O lines arranged as follows:
7
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134).
1996 Nov 25
V
V
I
I
P
T
I
O
SYMBOL
Port 0; 8-bit parallel port (P0.0-P0.7)
Port1; 8-bit parallel port (P1.0-P1.7)
Port 2; 4-bit parallel port (P2.0-P2.3)
SCLK ; I
stg
DD
I
tot
8-bit microcontroller with I
FUNCTIONAL DESCRIPTION
LIMITING VALUES
‘Piggy-back’ version PCF84C00B
ROM-less version PCF84C00T
Data memory
I/O facilities
2
C-bus (serial I/O) clock line
supply voltage
all input voltages
DC input current
DC output current
total power dissipation
storage temperature
PARAMETER
2
C-bus interface
9
6.5
A positive-going signal on the RESET input/output:
A negative-going signal on the RESET input/output:
INT/T0; External interrupt and test input. When used as
a test input, it can be directly tested by conditional
branch instructions JT0 and JNT0.
T1; Test input which can alter program sequences when
tested by conditional jump instructions JT1 and JNT1.
T1 also functions as an input to the 8-bit timer/event
counter.
Sets the program counter to zero
Selects location 0 of memory bank 0 and register bank 0
Sets the stack pointer to zero (000); pointing to RAM
address 8
Disables the interrupts (external, timer and I
Stops the timer/event counter, then sets it to zero
Sets the timer prescaler to divide by 32
Resets the timer flag
Sets all ports except P2.3 to input mode
Sets the I
disables the I
Cancels Idle and Stop mode.
Sets P2.3/SDA and SCLK to HIGH after a maximum of
30 clock pulses
Sets the I
disables the I
clock pulses
Starts program execution after 1866 clock pulses.
CONDITIONS
Reset
2
2
C-bus interface to slave receiver mode and
C-bus interface to slave receiver mode and
2
2
C-bus interface
C-bus interface after a maximum of 30
0.8
0.5
10
10
65
MIN.
Product specification
+8
V
+10
+10
125
+150
PCF84C00
DD
MAX.
+0.5 V
2
C-bus)
V
mA
mA
mW
C
UNIT