M41T81M ST Microelectronics, M41T81M Datasheet - Page 12

• Manufacturer Part Number: M41T81M
• Description: SERIAL ACCESS RTC WITH ALARMS
• Manufacturer: ST Microelectronics

M41T81
READ Mode
In this mode the master reads the M41T81 slave
after setting the slave address (see Figure 14,
page 12). Following the WRITE Mode Control Bit
(R/W=0) and the Acknowledge Bit, the word ad-
dress 'An' is written to the on-chip address pointer.
Next the START condition and slave address are
repeated followed by the READ Mode Control Bit
(R/W=1). At this point the master transmitter be-
comes the master receiver. The data byte which
was addressed will be transmitted and the master
receiver will send an Acknowledge Bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an Acknowledge Clock. The
M41T81 slave transmitter will now place the data
byte at address An+1 on the bus, the master re-
ceiver reads and acknowledges the new byte and
the address pointer is incremented to “An+2.”
Figure 13. Slave Address Location
Figure 14. READ Mode Sequence
12/28
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
S
ADDRESS
SLAVE
DATA n+X
START
ADDRESS (An)
WORD
P
1
1
SLAVE ADDRESS
S
0
ADDRESS
1
SLAVE
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume due
to a Stop Condition or when the pointer increments
to any non-clock address (08h-13h).
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41T81 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 15, page 13).
0
0
0
R/W
A
DATA n
AI00602
DATA n+1
AI00899