PCF8579 Philips Semiconductors, PCF8579 Datasheet - Page 8

• Manufacturer Part Number: PCF8579
• Description: LCD column driver for dot matrix graphic displays
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7
The PCF8579 column driver is designed for use with the
PCF8578. Together they form a general purpose LCD dot
matrix chip set.
Typically up to 16 PCF8579s may be used with one
PCF8578. Each of the PCF8579s is identified by a unique
4-bit hardware subaddress, set by pins A0 to A3.
The PCF8578 can operate with up to 32 PCF8579s when
using two I
addresses are set by the logic level on input SA0.
7.1
The bias levels required to produce maximum contrast
depend on the multiplex rate and the LCD threshold
voltage (V
which the LCD exhibits 10% contrast. Table 1 shows the
optimum voltage bias levels for the PCF8578/PCF8579
chip set as functions of V
with the discrimination ratios (D) for the different multiplex
rates. A practical value for V
V
as graphs.
Table 1 Optimum LCD bias voltages
1997 Apr 01
-------- -
V
-------- -
V
-------- -
V
-------- -
V
V
-------- -
V
off(rms)
D
V
V
V
V
V
---------------------- -
V
---------------------- -
PARAMETER
LCD column driver for dot matrix graphic
displays
op
op
op
op
op
th
off rms
on rms
2
3
4
5
FUNCTIONAL DESCRIPTION
V
V
=
op
op
V
---------------------- -
V
Multiplexed LCD bias generation
with V
off rms
on rms
th
2
). V
C-bus slave addresses. The two slave
th
th
. Figure 4 shows the first 4 rows of Table 1
is typically defined as the RMS voltage at
0.739
0.522
0.478
0.261
0.297
0.430
1.447
3.370
1 : 8
op
(V
op
MULTIPLEX RATE
op
1 : 16
0.800
0.600
0.400
0.200
0.245
0.316
1.291
4.080
is obtained by equating
= V
DD
1 : 24
0.830
0.661
0.339
0.170
0.214
0.263
1.230
4.680
V
LCD
), together
1 : 32
0.850
0.700
0.300
0.150
0.193
0.230
1.196
5.190
8
7.2
At power-on the PCF8579 resets to a defined starting
condition as follows:
1. Display blank (in conjunction with PCF8578)
2. 1 : 32 multiplex rate
3. Start bank, 0 selected
4. Data pointer is set to X, Y address 0, 0
5. Character mode
6. Subaddress counter is set to 0
7. I
Data transfers on the I
following power-on, to allow completion of the reset action.
V bias
V op
V
Fig.4
bias
2
C-bus is initialized.
1.0
0.8
0.6
0.4
0.2
Power-on reset
= V
0
2
, V
V
bias
3
, V
4
/V
, V
op
5
1:8
. See Table 1.
as a function of the multiplex rate.
2
C-bus should be avoided for 1 ms
1:16
V 2
V 3
V 4
V 5
Product specification
1:24
multiplex rate
PCF8579
MSA838
1:32