STLC5411 ST Microelectronics, STLC5411 Datasheet - Page 24

• Manufacturer Part Number: STLC5411
• Description: 2B1Q U INTERFACE DEVICE
• Manufacturer: ST Microelectronics

STLC5411
code is sent permanently by the UID until a new
status change occurs in RXACT register.
C1 bit is sent first to the line.
LINE CODING AND FRAME FORMAT
2B1Q coding rule requires that binary data bits
are grouped in pairs so called quats (see Tab.2).
Each quat is transmitted as a symbol, the magni-
tude of which may be 1 out 4 equally spaced volt-
age levels (see Fig. 6). +3 quat refers to the
nominal pulse waveform specified in the ANSI
standard. Other quats are deduced directly with
respect of the ratio and keeping of the waveform.
The frame format used in UID follows ANSI speci-
fication (see Tab. 3 and 4). Each complete frame
consists of 120 quats, with a line baud rate of 80
kbaud, giving a frame duration of 1.5ms. A nine
quats lenght sync-word defines the framing
boundary. Furthermore, a Multiframe consisting of
8 frames is defined in order to provide sub-chan-
nels within the spare bits M1 to M6. Inversion of
the syncword defines the multiframe boundary. In
LT, the transmit multiframe starting time may be
synchronized by means of a 12 ms period of time
pulse on the SFSx pin selected as an input (bit
SFS in CR2); If SFSx is selected as an output,
SFSx provides a square wave signal with the ris-
ing edge indicating the multiframe starting time. In
NT, the transmit multiframe starting time is pro-
vided on SFSx output by the rising edge of a 12
ms period of time square wave signal. LT or NT,
when pin 25 is selected as SFSr by mean of bit
ESFr in CR4, SFSr is a square wave open drain
output indicating the received superframe on the
line. (see figure 7). Prior to transmisssion, all
data, with the exception of the sync-word,is
scrambled using a self-synchronizing scrambler
to perform the specified 23rd-order polynomial.
Descrambling is included in the receiver. Polyno-
mial is different depending on the direction LT to
NT or vice versa.
TRANSMIT SECTION
Data transmitted to the line consists of the 2B+D
channel data received from the Digital Interface
through an elastic data buffer allowing any phase
deviation with the line, the activation/deactivation
bits (M4) from the on-chip activation sequencer,
the CRC code plus maintenance data (eoc chan-
nels) and other spare bits in the overhead chan-
nels (M4, M5, M6). Data is multiplexed and
scrambled prior to addition of the sync-word,
which is generated within the device. A pulse
waveform synthesizer then drives the transmit fil-
ter, which in turn passes the line signal to the line
driver. The differential line-driver Outputs, LO+,
LO- are designed to drive a transformer through
an external termination circuit. A 1:1.5 trans-
former designed as shown in the Application sec-
24/72
tion, results in a signal amplitude of 2.5V pk
nomince on the line for single quats of the +3
level. (see output pulse template fig.8). Short-cir-
cuit protection is included in the output stage;
over-voltage protection must be provided exter-
nally.
In LT applications, the Network reference clock
given by the FSa 8kHz clock input synchronizes
the transmitted data to the line. The Digital Inter-
face normally accepts BCLK and FSa signals
from the network, requiring the selection of Slave
Mode in CR1. A Digital Phase-Locked Loop
(DPLL#1) on the UID allows the SCLK frequency
to be plesiochronous with respect to the network
reference clock (8 kHz FSa input). With a toler-
ance on the XTAL1 oscillator of 15.36 MHz +/-
100 ppm, the lock-in range of DPLL1 allows the
network clock frequency to deviate up to +/-
50ppm from nominal.
In LT, if DSI is selected in Master mode, (Mi-
crowire only, bit CMS = 1 in CR1), BCLK and FSa
signals are outputs frequency synchronized to
XTAL1 input, DPLL#1 is disabled.
In NT applications, data is transmitted to the line
with a phase deviation of half a frame relative to
the received data as specified in the ANSI stand-
ard.
RECEIVE SECTION
The receive input signal should be derived from
the transformer by a coupling circuit as shown in
the Application section. At the front end of the re-
ceive section is a continuous filter which limits the
noise bandwidth to approximately 100kHz. Then,
an analog pre-canceller provides a degree of
echo cancellation in order to limit the dynamic
range of the composite signal which noise band-
width limited by a 4th order Butterworth switched
capacitor low pass filter. After an automatic gain
control, a 13bits A/D converter then samples the
composite received signal before the echo can-
cellation from local transmitter by means of an
adaptive digital transversal filter. The attenuation
and distortion of the received signal from the far-
end, caused by the line, is equalized by a second
adaptive digital filter configured as a Decision
Feedback Equalizer (DFE), that restores a flat
channel response with maximum received eye
opening over a wide spread of cable attenuation
characteristics.
A timing recovery circuit based on a DPLL (Digital
Phase-Locked Loop) recovers a very low-jitter
clock for optimum sampling of the received sym-
bols. The 15.36MHz crystal oscillator (or the logic
level clock input) provides the reference clock for
the DPLL. In NT configuration, SCLK output pro-
vides a very low jitterized 15.36MHz clock syn-
chronized from the line.
Received data is then detected and flywheel syn-
chronization circuit searches for and locks onto