TC7126 TelCom, TC7126 Datasheet - Page 6

• Manufacturer Part Number: TC7126
• Description: 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS
• Manufacturer: TelCom

TC7126
TC7126A
For a constant V
integrating resistor and capacitor values, as long as they are
stable during a measurement cycle. Noise immunity is an
inherent benefit. Noise spikes are integrated, or averaged,
to zero during integration periods. Integrating ADCs are
immune to the large conversion errors that plague succes-
sive approximation converters in high-noise environments.
Interfering signals with frequency components at multiples
of the averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set to a
multiple of the 50 Hz/60 Hz power line period.
ANALOG SECTION
slope cycles discussed above, the TC7126A design incor-
porates an auto-zero cycle. This cycle removes buffer
amplifier, integrator, and comparator offset voltage error
terms from the conversion. A true digital zero reading results
without external adjusting potentiometers. A complete con-
version consists of three phases:
Auto-Zero Phase
is disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
(ground) to establish a zero input condition. Additional
3-222
V
The dual-slope converter accuracy is unrelated to the
In addition to the basic integrate and deintegrate dual-
(1) Auto-zero phase
(2) Signal integrate phase
(3) Reference integrate phase
During the auto-zero phase, the differential input signal
Figure 2. Normal-Mode Rejection of Dual-Slope Converter
IN
30
20
10
0
= V
0.1/t
R
t
t
RI
SI
IN
:
.
INPUT FREQUENCY
t = MEASUREMENT PERIOD
1/t
10/t
analog gates close a feedback loop around the integrator
and comparator. This loop permits comparator offset volt-
age error compensation. The voltage level established on
C
phase residual is typically 10 V to 15 V.
periods.
Signal Integration Phase
tial inputs connect to V
signal is integrated for a fixed time period. The TC7126A
signal integration period is 1000 clock periods, or counts.
The externally-set clock frequency is 4 before clocking the
internal counters. The integration time period is:
where f
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
power supply common, V
mon.
phase. The sign bit is a true polarity indication, in that signals
less than 1 LSB are correctly determined. This allows
precision null detection limited only by device noise and
auto-zero residual offsets.
Reference Integrate Phase
V
connected across the previously-charged reference capaci-
tor. Circuitry within the chip ensures that the capacitor will be
connected with the correct polarity to cause the integrator
output to return to zero. The time required for the output to
return to zero is proportional to the input signal and is
between 0 and 2000 internal clock periods. The digital
reading displayed is:
DIGITAL SECTION
sary to directly drive a 3-1/2 digit LCD. An LCD backplane
driver is included. The backplane frequency is the external
clock frequency
backplane frequency is 60 Hz with a 5V nominal amplitude.
IN
AZ
ANALOG-TO-DIGITAL CONVERTERS
–
The auto-zero cycle length is 1000 to 3000 clock
The auto-zero loop is entered and the internal differen-
t
The differential input voltage must be within the device
Polarity is determined at the end of signal integrate
The third phase is reference integrate, or deintegrate.
1000
The TC7126A contains all the segment drivers neces-
compensates for device offset voltages. The auto-zero
SI
is internally connected to analog common and V
=
OSC
f
V
OSC
V
= external clock frequency.
4
REF
IN
1000,
800. For 3 conversions per second the
TELCOM SEMICONDUCTOR, INC.
IN
+
IN
and V
–
should be tied to analog com-
IN
–
. The differential input
3-1/2 DIGIT
IN
+
is