MAX1169 Maxim Integrated Products, MAX1169 Datasheet - Page 5

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MAX1169

Manufacturer Part Number
MAX1169
Description
58.6ksps / 16-Bit / 2-Wire Serial ADC in a 14-Pin TSSOP
Manufacturer
Maxim Integrated Products
Datasheet

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ELECTRICAL CHARACTERISTICS (continued)
(AV
erence applied to REF, REFADJ = AV
Note 1: DC accuracy is tested at AV
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
Note 3: Offset nullified.
Note 4: One sample is achieved every 18 clocks in continuous conversion mode:
Note 5: The track/hold acquisition time is two SCL cycles as illustrated in Figure 11:
Note 6: A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and
Note 7: ADC performance is limited by the converter’s noise floor, typically 225µV
Note 8:
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figure 1b and Figure 2)
Serial Clock Frequency
Hold Time (Repeated) Start
Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
Rise Time of SCL Signal After
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
C ap aci ti ve Load for E ach Bus Li ne
Pulse Width of Spike Suppressed
DD
= +4.75V to +5.25V, DV
f
PSRR
by power-supply rejection test.
offset have been calibrated.
50ns in fast mode.
t
SAMPLE
ACQ
PARAMETER
= ×
=
2
[
=
V (5.25V)- V (4.75V)
FS
_______________________________________________________________________________________
1 clocks
f
SCL
8
1
f
SCL
5.25V - 4.75V
DD
+
FS
= +2.7V to +5.5V, f
t
C
58.6ksps, 16-Bit, 2-Wire Serial ADC
DD
ONV
DD
SYM B O L
t
t
t
t
t
HD, STA
HD, DAT
SU, DAT
SU, STO
SU, STA
, C
f
t
t
t
SCLH
t
t
t
HIGH
RCL1
t
LOW
RCL
RDA
FDA
FCL
C
t
= +5.0V and DV
SP
REF
]
B
-1
×
= 10µF, T
V
2
REF
N
(Note 11)
(Note 9)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
SCL
where N is the number of bits ( ).
A
= 1.7MHz (33% duty cycle), f
= T
DD
MIN
= +3.0V. Performance at power-supply tolerance limits is guaranteed
to T
CONDITIONS
MAX
, unless otherwise noted. Typical values are at T
P-P
in a 14-Pin TSSOP
SAMPLE
16
.
= 58.6ksps, V
MIN
160
320
120
160
160
10
10
20
20
20
20
0
REF
TYP
= +4.096V, external ref-
MAX
150
160
160
160
400
1.7
80
80
10
A
= +25°C.)
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
5

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