LM1237AAF/NA National Semiconductor, LM1237AAF/NA Datasheet - Page 37

• Manufacturer Part Number: LM1237AAF/NA
• Description: 150 MHz I2C Compatible RGB Preamplifier with Internal 254 Character OSD and 4 DACs
• Manufacturer: National Semiconductor

Pre-Amplifier Interface Registers
DAC 3 Register
Register Name (address): DAC3CTRL (0x8436)
DAC 4 Register
Register Name (address): DAC4CTRL (0x8437)
DAC Config, OSD Contrast & DC Offset Register
Register Name (address): DACOSDDCOFF (0x8438)
Global Video Control Register
Register Name (address): GLOBALCTRL (0x8439)
PLL Range Register
Register Name (address): PLLFREQRNG (0x843E)
Bits 7–0
Bits 7–0
Bits 7–0
Bits 2–0
Bits 4–3
Bit 5
Bit 6
Bit 7
Bit 0
Bit 1
Bits 1–0
Bit 2
RSV
RSV
RSV
RC7
BA7
7
7
7
7
7
DCF1
This register determines the output of DAC 2. The full-scale output is determined by bit 5 of the DAC
Config, OSD Contrast & DC Offset Register.
This register determines the output of DAC 3. The full-scale output is determined by bit 5 of the DAC
Config, OSD Contrast & DC Offset Register.
This register determines the output of DAC 4. The output of this DAC can be scaled and mixed with the
outputs of DACs 1–3 as determined by bit 6 of the DAC Config, OSD Contrast & DC Offset Register.
These determine the DC offset of the three video outputs, blue, red and green.
These determine the contrast of the internally generated OSD.
When this bit is a 0, the full-scale outputs of DACs 1–3 are 4.5V. When it is a 1 the full-scale level is
2.5V.
When this bit is a 0, the DAC 4 output is independent. When it is a 1, the DAC 4 output is scaled by
50% and added to the outputs of DACs 1–3.
Reserved and should be set to zero.
When this bit is a 1, the video outputs are blanked (set to black level). When it is a 0, video is not
blanked.
When this bit is a 1, the analog sections of the preamplifier are shut down for low power consumption.
When it is a 0, the analog sections are enabled.
These determine the optimum frequency range of the Phase Locked Loop. Please see Table 3 for
recommended register values for various horizontal scan rates.
This is the Vertical Blanking register. When this bit is a 1, vertical blanking is gated to the video outputs.
When set to a 0, the video outputs do not have vertical blanking.
RC6
RSV
RSV
BA6
6
6
6
6
6
CLMP
DCF0
RSV
RC5
BA5
5
5
5
5
5
OSD1
RSV
RSV
RC4
BA4
4
4
4
4
4
(Continued)
37
OSD0
OOR
RC3
RSV
BA3
3
3
3
3
3
RC2
DC2
RSV
BA2
VBL
2
2
2
2
2
PFR1
RC1
DC1
BA1
PS
1
1
1
1
1
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PFR0
RC0
DC0
BA0
BV
0
0
0
0
0