CS5106 Cherry Semiconductor Corporation, CS5106 Datasheet - Page 7

• Manufacturer Part Number: CS5106
• Description: Multi-Feature/ Synchronous plus Auxiliary PWM Controller
• Manufacturer: Cherry Semiconductor Corporation

PACKAGE LEAD #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
9
PROGRAM
LEAD SYMBOL
SYNC
ENABLE
GATE2B
DLYSET
SYNC
RAMP2
GATE1
GATE2
FADJ
I
V
Gnd
V
V
V
LIM2
FB1
FB2
CC
SS
OUT
IN
Package Lead Description: continued
the auxiliary power supply output voltage is fed to this lead. A voltage less
than RAMP1+0.13 on V
In addition, this lead is fed to a divide by ten resistor divider and compared to
1.2V nominal at the positive side of the error amplifier.
V
and all main power is derived from V
drives the auxiliary transformer.
which drives the main transformer.
the gate drive transformer used for synchronous rectification.
the main power supply output voltage is fed to this lead. A voltage less than
RAMP2+0.13 on V
with respect to current in the primary side of the main trans former is usually
represented on this lead. A voltage exceeding V
cause GATE2 to go low and GATE2B to go high.
age exceeding 1.2V nominal on I
to go high. A voltage exceeding 1.4V nominal on I
low and GATE2B to go high for at least two clock cycles.
DLYSET to ground sets the non-overlap time to 45ns nominal.
clock frequency to 512kHz nominal.
is in phase with GATE1. This signal can be used to synchronize other power
supplies.
+10%, -15% by the onset of positive edges of an external clock occurring on the
SYNC
quency by +25%, -35% the external clock is ignored and the internal clock free
runs.
GRAM has at least 20µA min. of available source current.
allow GATE1, GATE2 and GATE2B to switch. If PROGRAM is LOW then a
HIGH on ENABLE will allow GATE1, GATE2 and GATE2B to switch. If
ENABLE is left floating, it will pull up to a HIGH level. ENABLE has at least
100µA (min) of available source current.
Voltage Feedback Lead for the Auxiliary PWM. A voltage which represents
V
V
Auxiliary PWM gate drive lead. This output normally drives the FET which
Ground lead.
Synchronous PWM gate drive lead. This output normally drives the FET
Synchronous PWM gate drive lead. This output normally drives the FET for
Voltage feedback lead for the synchronous PWM. A voltage which represents
Current ramp input lead for the synchronous PWM. A voltage which is linear
Pulse by pulse over current protection lead for the synchronous PWM. A volt-
GATE2, GATE2B non-overlap time adjustment lead. A 27k½ resistor from
Frequency adjustment lead. A 27k½ resistor from FADJ to ground sets the
Clock output lead. This is a 50% duty cycle, 1V to 5V pulse whose rising edge
Clock synchronization lead. The internal clock frequency can be adjusted
ENABLE programming input. See ENABLE for programming states. PRO-
PWM enable input. If PROGRAM is HIGH then a LOW on ENABLE will
SS
SS
CC
> V
power/feedback input lead. See V
power input lead. This input runs off a Zener referenced supply until
IN
CC
lead. If the external clock frequency is out side the internal clock fre-
. Then an internal diode which runs between V
7
FB2
will cause GATE2 to go low and GATE2B to go high.
FB1
will cause GATE1 to go low.
FUNCTION
LIM2
will cause GATE2 to go low and GATE2B
SS
CC
.
for description of power operation.
FB2
LIM2
- 0.13 on RAMP2 will
will cause GATE2 to go
SS
and V
CC
turns on