DAC16 Analog Devices, DAC16 Datasheet - Page 10

• Manufacturer Part Number: DAC16
• Description: 16-Bit High Speed Current-Output DAC
• Manufacturer: Analog Devices

DAC16
DAC16 Noise Performance
The novel architecture employed in the DAC16 yields very low
wideband noise. Figure 26 illustrates the circuit configuration
for evaluating the DAC16’s noise performance. An OP27 is
used as the DAC16’s output I–V converter which is configured
to produce a 5 V full-scale output voltage. The output of the
OP27 was then capacitively coupled to an OP37 stage config-
ured in a gain of 101. Note that the techniques for reducing
wideband noise of the voltage reference and the DAC’s internal
reference amplifier were used. As a result of these techniques,
the DAC16 exhibited a full-scale output noise spectral density
of 31 pA/ Hz at 1 kHz.
Digital Feedthrough and Data Skew
The DAC16 features a compound DAC architecture where the
5 most significant bits utilize 31 identical, segmented current
sources to obtain optimal high speed settling at major code tran-
sitions. Although every effort has been made to equalize the
speeds at which the DAC switches operate, there exists finite
skew in the MSB DAC switches.
As with any converter product, a high speed digital-to-analog
converter is forced to exist on the frontier between the noisy en-
vironment of high speed digital logic and the sensitive analog
domain. The problems of this interlace are particularly acute
when demands of high speed (greater than 10 MHz switching
times) and high precision are combined. No amount of design
effort can perfectly isolate the analog portions of a DAC from
the spectral components of a digital input signal with a 2 ns rise
time. Inevitably, once this digital signal is brought onto the chip,
some of its higher frequency components will find their way to
the sensitive analog nodes, producing a digital feedthrough
glitch. To minimize the exposure to this effect, the DAC16 was
designed to omit intentionally the on-board latches that are usu-
ally included in many slower DACs. This not only reduces the
overall level of digital activity on chip, it also avoids bringing a
latch clock pulse onto the IC, whose opposite edge inevitably
produces a substantial glitch, even when the DAC is not sup-
posed to be changing codes.
The DAC16 uses each digital input line to switch each current
segment in the DAC between the output diode-connected
transistor and the logic control transistor. If the input bits are
not changed simultaneously, or if the different DAC bits switch
0.1 F
+5V
10 F
REF02
+15V
0.1 F
DIGITAL +5V
PIN 3, DAC16
5k
R1
22 F
Figure 26. DAC16 Noise Measurement Test Circuit
47 F
CLK
EN
C1
5k
R2
–15V
C2
100nF
CERAMIC
DB0 – DB7
74AC11377
I
C
REF GND
REF
COMP
DIGITAL INPUT WORD
8
DAC16
–10–
–15V
8
10 F
DB8 – DB15
74AC11377
at different speeds, then the DAC output current will momen-
tarily take on some incorrect value. This effect is particularly
troublesome at the “carry points,” where the DAC output is to
change by only one LSB, but several of the larger current
sources must be switched to realize this change. Data skew can
allow the DAC output to move a substantial amount towards
full scale or zero (depending upon the direction of the skew)
when only a small transition is desired. The glitch-sensitive user
should be equally diligent about minimizing the data skew at the
DAC16’s inputs, particularly the five most significant bits. This
can be achieved by using the proper logic family and gate to
drive the DAC inputs, and keeping the interconnect lines be-
tween the latches and the DAC inputs as short and as well
matched as possible. Logic families that were empirically deter-
mined to operate well with the DAC16 are devices from the
74AC11xxx and 74ACT11xxx advanced CMOS logic families.
These devices have been purposely designed with improved lay-
out and tailored rise times for minimizing ground bounce and
digital feedthrough.
Deglitching
The output glitch of the DAC16 at the major carry (7FFE
7FFF
momentary output transition to the negative rail for approxi-
mately 200 ns. Due to the inherent low-pass or time-sampled
nature of many systems, this behavior in the DAC16 is not
noticeable and does not detract from overall performance. Some
applications however may prove so sensitive to glitch impulse
that reduction by an order of magnitude or more is required. In
order to realize low glitch impulses, some sort of sample-and-
hold amplifier-based deglitching scheme must be used.
There are high speed SHAs available with specifications suffi-
cient to deglitch the DAC16; however, most are hybrid in topol-
ogy at costs which can be prohibitive. A high performance, low
cost alternative shown in Figure 27 is a discrete SHA utilizing a
high speed monolithic op amp and high speed DMOS FET
switches.
This SHA circuit uses the inverting integrator structure. A
300 MHz gain-bandwidth product op amp, the AD841, is the
heart of this fast SHA. The time constant formed by the 200
resistor and the 100 pF capacitor determines the acquisition
time and also hand limits the output signal to eliminate slew-
induced distortion.
AGND
0.1 F
I
OUT
H
) is a not-insignificant 360 pA-sec, manifested as a
RESISTORS:
CADDOCK T912–5K–010–02 (OR EQUIVALENT)
5k , 0.01%, TC TRACK = 2 ppm/ C
OP27A
(2.49k
+15V
–15V
1.25k
R3
10 F
10 F
0.1 F
0.1 F
2)
V
0V TO +5V FS
OUT
REV. B
H
to