DSP56002RC40 Motorola Inc, DSP56002RC40 Datasheet - Page 4
DSP56002RC40
Manufacturer Part Number
DSP56002RC40
Description
24-BIT DIGITAL SIGNAL PROCESSOR
Manufacturer
Motorola Inc
Datasheet
1.DSP56002RC40.pdf
(110 pages)
- Current page: 4 of 110
- Download datasheet (717Kb)
Features
Peripheral and Support Circuits
Miscellaneous Features
iv
• Byte-wide host interface (HI) with Direct Memory Access (DMA) support (or
• SSI support:
• SCI for full duplex asynchronous communications (or three additional Port C
• One 24-bit timer/event counter (or one additional GPIO line)
• Double-buffered peripherals
• Up to twenty-five General Purpose Input/Output (GPIO) pins
• One non-maskable and two maskable external interrupt/mode control pins
• On-Chip Emulation (OnCE ) port for unobtrusive, processor speed-
• Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer
• Power-saving Wait and Stop modes
• Fully static, HCMOS design for specified operating frequency down to dc
• Three packages available:
fifteen Port B GPIO lines)
–
–
–
–
GPIO lines)
independent debugging
for the DSP core clock with a wide input frequency range (12.2 KHz to 80
MHz)
–
–
–
Supports serial devices with one or more industry-standard codecs, other
DSPs, microprocessors, and Motorola-SPI-compliant peripherals
Asynchronous or synchronous transmit and receive sections with separate
or shared internal/external clocks and frame syncs
Network mode using frame sync and up to 32 software-selectable time
slots
8-bit, 12-bit, 16-bit, and 24-bit data word lengths
132-pin Plastic Quad Flat Pack (PQFP); 1.1
144-pin Thin Quad Flat Pack (TQFP); 20 20 1.5 mm
132-pin Ceramic Pin Grid Array (PGA); 1.36 1.35 0.125 inches
DSP56002/D, Rev. 3
1.1 0.19 inches
MOTOROLA
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