SAA7201H Philips Semiconductors, SAA7201H Datasheet - Page 15

• Manufacturer Part Number: SAA7201H
• Description: Integrated MPEG2 AVG decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Video decoder
The video decoding unit provides all actions required for
compliant decoding of MPEG2 main level, main profile
coded video bit streams. The decoding process consists of
fixed and variable length decoding, run length decoding,
inverse quantization, inverse discrete cosine
transformation, motion compensation and interpolation.
In general the arithmetic decoding result is stored as
reference picture in the external memory.
Decoded B-frames are only stored for the conversion from
the frame coded macro block (MB) to the scanning line
format. In many cases a field storage is sufficient for this
conversion but in some cases the user might decide to use
a full frame storage to enable chroma frame up-conversion
or full performance 3 : 2 pull-down in 60 Hz systems.
Obviously when using less memory for the video decoding
process more memory is available for non-video decoding
tasks.
1997 Jan 29
handbook, full pagewidth
Integrated MPEG2 AVG decoder
buffer
input
from
VLD
Fig.7 Video decoding unit.
FLD
IZZ
from reference
memory
IQ
15
The Frame Buffer Management unit (FBM) manages the
allocation of frame buffers in external SDRAM for both
video decoding and display unit and can be programmed
to use less memory in not fully MP@ML bitstreams:
smaller pictures (e.g. 544
Apart from decoding compliant MPEG video streams the
decoder deals with some trick modes. Supported are field
or frame freeze at I or P pictures or freeze field on
B-pictures. In the latter case decoding will continue as a
background process and the output can be restarted at
any moment. When receiving non-compliant MPEG
streams the decoder can be switched to a scanning mode
in which only I or I + P frames are decoded while skipping
all other pictures. In the single step mode, the decoder
decodes just one frame and awaits a next step command.
The functional diagram of the video decoding unit is shown
in Fig.7.
IDCT
MC
INTERP
FBM
to external
memory
to display
unit
MGD327
576), simple profile, etc.
Objective specification
SAA7201