SAA7366T Philips Semiconductors, SAA7366T Datasheet - Page 6

• Manufacturer Part Number: SAA7366T
• Description: Bitstream conversion ADC for digital audio systems
• Manufacturer: Philips Semiconductors

Philips Semiconductors
recommended circuit the following applies: the inverting
operational amplifier inputs BIL/BIR are protected from
excessive voltages (currents) by diodes to V
These have absolute maximum ratings of I
with a safe practical limit of 2 mA. Given the input resistor
of 10 k , 2 mA diode current and the operation of the
operational amplifier a maximum signal (applied to the
input resistor) of 30 V can be handled safely. This level
represents an overload of 26 dB.
During overload the in-band portion of the waveform will be
correctly converted. The out-of-band portion will be limited
as detailed above.
Sigma-Delta modulator
The SAA7366 has two third order Sigma-Delta modulators
with a quantization noise floor of approximately 104 dB.
The scaling of the feedback has been optimized for stable
operation even during overload. Thus with a maximum
signal swing of 0 V to V
remains well behaved, i.e. it does not burst into random
oscillation. During overload the output is simply a clipped
version of the input. The gain of this stage is 4.95 dB.
Decimation filter
Decimation from 128f
stage is a comb filter, which decimates from 128 to 8f
The second stage, consists of 3 half-band filters, each
decimating by a factor of 2.
The overall characteristics are given in Table 1.
Table 1 Overall filter characteristics.
High-pass filter
An optional high-pass filter is provided to remove
unwanted DC components. The operation is selected
when HPEN is HIGH. The filter has the characteristics
given in Table 2.
May 1994
Pass band ripple 0 to 0.45f
Stop band
Dynamic range
Gain
Bitstream conversion ADC for
digital audio systems
ITEM
0.45 to 0.47f
0 to 0.42f
DC
0.55f
s
is performed in two stages. The first
DDA
s
CONDITION
on the input the digital output
s
s
Hz
s
IK
DDA
= 20 mA,
and V
VALUE
(dB)
3.87
110
0.1
0.5
60
SSA
s
.
.
6
Table 2 High-pass filter characteristics.
Serial interface
The serial interface provides 2 formats in both master and
slave modes (see Figs 3 and 4). In both modes the
interface provides up to 18 significant bits of output data
per channel.
During standby mode (STD = LOW) all interface pins are
in their high-impedance state. On recovery from standby
the serial data output SDO is held LOW until valid data is
available from the decimation filter. This time depends on
whether the high-pass filter is selected or not as follows:
HPEN = 0; T = 1024/f
HPEN = 1; T = 8192/f
Overload Detection Indication (OVLD)
The OVLD output is used to indicate whenever the data, in
either the left or right channel, is within 1 dB of the
maximum possible digital swing. When this condition is
detected the OVLD output is forced HIGH for at least 512f
cycles (10.6 ms at f
each infringement.
Standby mode (STD)
The STD pin activates a power saving mode when the
device function is not required. This pin can also be used
as a chip enable, as follows.
On a HIGH-to-LOW transition, of the STD pin, the internal
control circuitry starts a timed power-down sequence. This
takes approximately 32 system clock cycles to complete.
Transitions on STD which are shorter than 32 clock cycles
have an indeterminate effect. However, the device will
always recover correctly.
Pass band ripple
Pass band gain
Droop
Attenuation at DC
Dynamic range
ITEM
s
= 48 kHz). This time-out is reset for
s
s
, T = 21.3 ms when f
, T = 170.6 ms when f
at 0.00045f
at 0.00000036f
0 to 0.45f
CONDITION
Preliminary specification
s
s
s
SAA7366
s
s
= 48 kHz
= 48 kHz
VALUE
0.029
none
(dB)
116
0
40
s