XCV100 Xilinx, XCV100 Datasheet

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XCV100

Manufacturer Part Number
XCV100
Description
Virtex-E 1.8 V Field Programmable Gate Arrays
Manufacturer
Xilinx
Datasheet

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DS022-1 (v2.2) November 9, 2001
Features
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
Fast, High-Density 1.8 V FPGA Family
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Highly Flexible SelectI/O+™ Technology
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Differential Signalling Support
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Proprietary High-Performance SelectLink™
Technology
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Sophisticated SelectRAM+™ Memory Hierarchy
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* ZBT is a trademark of Integrated Device Technology, Inc.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Densities from 58 k to 4 M system gates
130 MHz internal performance (four LUT levels)
Designed for low-power operation
PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
Supports 20 high-performance interface standards
Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
Differential I/O signals can be input, output, or I/O
Compatible with standard differential devices
LVPECL and LVDS clock inputs for 300+ MHz
clocks
Double Data Rate (DDR) to Virtex-E link
Web-based HDL generation methodology
1 Mb of internal configurable distributed RAM
Up to 832 Kb of synchronous internal block RAM
True Dual-Port™ BlockRAM capability
Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
Designed for high-performance Interfaces to
External Memories
200 MHz ZBT* SRAMs
200 Mb/s DDR SDRAMs
Supported by free Synthesizable reference design
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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www.xilinx.com
1-800-255-7778
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Virtex™-E 1.8 V
Field Programmable Gate Arrays
Preliminary Product Specification
High-Performance Built-In Clock Management Circuitry
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Flexible Architecture Balances Speed and Density
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Supported by Xilinx Foundation™ and Alliance Series™
Development Systems
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SRAM-Based In-System Configuration
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Advanced Packaging Options
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0.18
100% Factory Tested
Eight fully digital Delay-Locked Loops (DLLs)
Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
Clock Multiply and Divide
Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input function
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
Internal 3-state bussing
IEEE 1149.1 boundary-scan logic
Die-temperature sensor diode
Further compile time reduction of 50%
Internet Team Design (ITD) tool ideal for
million-plus gate density designs
Wide selection of PC and workstation platforms
Unlimited re-programmability
0.8 mm Chip-scale
1.0 mm BGA
1.27 mm BGA
HQ/PQ
m
m 6-Layer Metal Process
Module 1 of 4
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XCV100 Summary of contents

Page 1

... ZBT is a trademark of Integrated Device Technology, Inc. © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. ...

Page 2

... XCV100E 128,236 32,400 XCV200E 306,393 63,504 XCV300E 411,955 82,944 XCV400E 569,952 129,600 XCV600E 985,882 186,624 XCV1000E 1,569,178 331,776 XCV1600E 2,188,742 419,904 XCV2000E 2,541,952 518,400 XCV2600E 3,263,755 685,584 XCV3200E 4,074,387 876,096 Virtex-E Compared to Virtex Devices The Virtex-E family offers up to 43,200 logic cells in devices up to 30% faster than the Virtex family ...

Page 3

... SPROM (mas- ter serial mode), or can be written into the FPGA (SelectMAP™, slave serial, and JTAG modes). The standard Xilinx Foundation Series™ and Alliance Series™ Development systems deliver complete design support for Virtex-E, covering every aspect from behavioral ...

Page 4

... Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4). • Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4). • Corrected pair 18 in Table 75 (Module “AO in the XCV1000E, XCV1600E“. Module Temperature Range C = Commercial ( +85 C) ...

Page 5

... Revised footnote for Table 14. 2/12/01 1.9 • Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and XCV2000E devices. • Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices. • Revised Table 62 to include pinout information for the XCV400E and XCV600E devices in the BG560 package. • ...

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