Z8018520FSC Zilog., Z8018520FSC Datasheet
Z8018520FSC
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Z8018520FSC Summary of contents
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Zilog FEATURES ROM UART Part (KB) Baud Rate Z80185 512 Kbps Z80195 0 512 Kbps 100-Pin QFP Package 5.0-Volt Operating Range Low-Power Consumption +70 C Temperature Range GENERAL DESCRIPTION The Z80185 and Z80195 are ...
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Zilog TIMING DIAGRAMS (Continued) 16-Bit Address Bus Processor 8-Bit Data Bus Power Controller TxD, EMSCC RxD Parallel Ports (2) Including IEEE Bidirectional Centronics Controller 16-Bit Programmable TOUT Reload Timers (2) CLK/TRG Figure 1. Z80185/195 Functional Block Diagram ...
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Zilog PIN DESCRIPTION 100 /INT1 1 /INT2 A15 A10 A11 A12 VSS A13 A14 20 A16 ...
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Zilog ABSOLUTE MAXIMUM RATINGS Symbol Description Min V Supply Voltage –0 Input Voltage –0 Operating Temp. 0 OPR T Storage Temp. –55 STG Notes: Voltage on all pins with respect to GND. Permanent LSI damage may ...
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Zilog DC CHARACTERISTICS V = 5.0V 10 over specified temperature range, unless otherwise noted Symbol Item V Input “H” Voltage IH V Input “L” Voltage IL V Output “H” Voltage OH V Output “L” Voltage ...
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Zilog TIMING DIAGRAMS Z8S180 MPU Timing Opcode Fetch Cycle ø Address 19 /WAIT 7 /MREQ /IORQ /RD 9a /WR / Data IN Data OUT 49 48 /RESET 54 (Opcode Fetch Cycle, Memory ...
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Zilog TIMING DIAGRAMS (Continued) Ø /INTI 33 /NMI /M1 [1] /IORQ [1] /Data IN [1] /MREQ [2] /RFSH [ /BUSREQ /BUSACK Address Data /MREQ, /RD, /WR, /IORQ /HALT Notes: [1] During /INT0 acknowledge cycle [2] During ...
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Zilog I/O Read Cycle Address 28 /IROQ 9 /RD /WR Ø TOUT//DREQ (At level sense) TOUT//DREQ (At edge sence) ST DMA Control Signals [1] tDRQS and tDRQH are specified for the rising edge of clock followed by ...
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Zilog TIMING DIAGRAMS (Continued) Ø TOUT/DREQ SLP Instruction Fetch T3 T1 Ø /INTi /NMI A18-A0 /MREQ, /M1 /RD /HALT DS971850301 Timer Data Reg = 0000H 47 Figure 8. Timer ...
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Zilog CSI/O Clock Transmit Data (Internal Clock) Transmit Data (External Clock) Receive Data (Internal Clock) Receive Data (External Clock tcyc 59 60 11.5 tcyc 16.5 ...
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Zilog TIMING DIAGRAMS (Continued) 63 /MREQ /RAMCS /ROMCS /IORQ 64 /IOCS 51 EXTAL VIH1 VIH1 VIL1 Figure 12. External Clock Rise Time and Fall Time DS971850301 Figure 11. /ROMCS ...
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Zilog AC CHARACTERISTICS 10 0V for outputs over DD SS specified temperature range, unless otherwise noted. No. Symbol Parameter 1 tcy Clock Cycle Time 2 tCHW Clock “H” Pulse Width 3 ...
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Zilog AC CHARACTERISTICS (Continued) No. Symbol Parameter 28a tIOD PHI Falling to IORQ Falling Delay IOC = 1) 28b tIOD PHI Rising to IORQ Fallin g Delay (IOC =0) 29 tIOD2 PHI Falling to IORQ Rising Delay 30 tIOD3 M1 ...
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Zilog AC CHARACTERISTICS (Continued) Read/Write External Bus Master Timing Address A7-A0 /IORQ /RD Data /WR Data Figure 14. Read/Write External Bus Master Timing ...
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Zilog AC CHARACTERISTICS (Continued) General-Purpose I/O Timing Port Timing Parameters referenced in Figure 15 appear in the following Tables. Note: Port 2 timing is different, even when Bidirec- tional Centronics feature is not in active use. I/O Port Timing (Output) ...
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Zilog I/O Port Timing No. Symbol Parameter A1 TdWR (PIA) Data Valid Delay from WR Rise External Bus Master Timing No. Symbol Parameter B1 TsA(wf) Address Valid (rf) RD Fall Time B2 TsIO(wf) IORQ Fall to WR ...
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Zilog AC CHARACTERISTICS (Continued) EMSCC Timing Ø /WR /RD Wait /INT EMSCC Timing Parameters No. Symbol 1 TdWR(W) 2 TdRD(W) 6 TdPC(INT) DS971850301 Figure 16. EMSCC AC ...
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Zilog EMSCC General Timing Diagram PCLK Wait /RTxC, /TRxC Receive 4 RxD /TRxC, /RTxC Transmit TxD 13 /TRxC Output /RTxC /TRxC /CTS, /DCD ...
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Zilog AC CHARACTERISTICS (Continued) EMSCC General Timing No. Symbol 2 TdPC(W) 3 TsRxC(PC) 4 TsRxD(RxCr) 5 ThRxD(RxCr) 6 TsRxD(RxCf) 7 ThRxD(RxCf) 10 TsTxC(PC) 11 TdTxCf(TXD) 12 TdTxCr(TXD) 13 TdTxD(TRX) 14 TwRTxh 15 TwRTxI 16a TcRTx 16b TxRx(DPLL) 17 TcRTxx 18 ...
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Zilog EMSCC System Timing Diagram /RTxC, /TRxC Receive /W/REQ Wait /INT /RTxC, /TRxC Transmit Wait /INT /CTS, /DCD /INT Figure 18. EMSCC System ...
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Zilog AC CHARACTERISTICS (Continued) EMSCC System Timing No. Symbol 2 TdRxC(W) 4 TdRxC(INT) 6 TdTxC(W) 8 TdTxC(INT) 10 TdExT(INT) Notes: [1] Open-drain output, measured with open-drain test load. [2] /RxC is /RTxC or /TRxC, whichever is supplying the receive clock. ...
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Zilog AC CHARACTERISTICS (Continued) Port 2 Output Control Output Control Input Port 2 Input Figure 20. P1284 Bidirectional Centronics Interface Timing P1284 Bidirectional Centronics Interface Timing No. Parameter 1 CLK High to Port 2 Output 2 CLK High to Control ...
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Zilog PIN DESCRIPTIONS Z80185 CPU Signals A0-A19. Address Bus (input/output, active High, tri-state). A0-A19 is a 20-bit address bus that provides the address for memory data bus cycles Mbyte, and I/O data bus cycles ...
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Zilog /INT1, /INT2. Maskable Interrupt Requests 1 and 2 inputs, active Low). These signals are generated by external I/O devices. The CPU will honor these requests at the end of the current instruction cycle as long as the /NMI, /BUSREQ, ...
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Zilog PIN DESCRIPTIONS (Continued) EMSCC Signals /RTS. Request to Send (output, active Low). When the Request to Send (RTS) bit in Write Register 5 is set, the /RTS signal goes Low. When the RTS bit is reset in the Asynchronous ...
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Zilog System Control Signals ST. Status (output, active High). This signal is used with the /M1 and /HALT output to indicate the nature of each CPU machine cycle. /RESET. Reset Signal (input, active Low). /RESET signal is used for initializing ...
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Zilog Z80185 MPU FUNCTIONAL DESCRIPTION The Z80185 includes a Zilog Z8S180 MPU (Static Z80180 MPU). This allows software code compatibility with exist- ing Z80/Z180 software code. The following is an overview of the major functional units of the Z80185. The ...
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Zilog Timing & Clock Ø Generator 16-Bit Programmable TOUT/ Reload Timers /DREQ (2) /RTS0/TxS Clocked /CTS0/RxS Serial I/O Port CKA0/CKS MMU A19- Bus State Control CPU DMACs Asynchronous ...
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Zilog Z80185 MPU FUNCTIONAL DESCRIPTION (Continued) DMA Controller The two DMA channels of the Z80185 can transfer data to or from the EMSCC channel, the parallel interface, the async ports external device. The I/O device encod- ing in ...
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Zilog FIFO and Receiver Operation The 4-byte Receive FIFO is used to buffer incoming data to reduce the incidence of overrun errors. When the RE bit is set in the CNTLA register, the RXA pin is monitored for a Low ...
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Zilog Z80185 MPU FUNCTIONAL DESCRIPTION (Continued) Baud Rate Generator The Baud Rate Generator (BRG) has two modes. The first is the same as in the Z80180. The second is a 16-bit down counter that divides the processor clock by the ...
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Zilog /M1 The /M1 generation logic of the Z80180 allows the use of logic analyzer disassemblers that rely on /M1 identifying the start of each instruction. If the MIE bit is set to 1, the processor does not refetch an ...
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Zilog Z8S180 POWER-DOWN MODES The following is a detailed description of the enhance- ments to the Z8S180 from the standard Z80180 in the areas of STANDBY, IDLE, and STANDBY-QUICK RECOVERY modes. Add-On Features There are five different power-down modes. SLEEP ...
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Zilog STANDBY Mode Exit with BUS REQUEST Optionally, if the BREXT bit (D5 of CPU Control Register) is set to 1, the Z8S180 exits STANDBY mode when the /BUSREQ input is asserted; the crystal oscillator is then restarted. An internal ...
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Zilog IDLE Mode IDLE mode is another power-down mode offered by the Z8S180. To enter IDLE mode: 1. Set D6 and and 1, respectively. 2. Set the I/O STOP bit (D5 of ICR, I/O Address = 3FH) ...
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Zilog Z8S180 MPU REGISTER MAP Notes: Registers listed in boldface type represent new registers added to the Z8S180. All register addresses not listed are Reserved. Register Name ASCI Control Register ASCI Control Register ASCI ...
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Zilog Z8S180 MPU REGISTERS ASCI CHANNELS CONTROL REGISTERS CNTLA0 MPE Bit RE Upon RESET 0 0 R/W R/W R/W CNTLA1 Bit MPE RE TE Upon RESET R/W R/W R/W R/W DS971850301 ...
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Zilog CNTLB0 /CTS/ Bit MPBT MP Upon Reset Invalid 0 R/W R/W R/W † /CTS - Depending on the condition of /CTS pin Cleared to 0. General Divide Ratio (Divide Ratio = 10) SS, 2, ...
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Zilog ASCI CHANNELS CONTROL REGISTERS (Continued) CNTLB1 Bit MPBT MP Upon Reset Invalid 0 R/W R/W R/W General Divide Ratio (Divide Ratio = 10) SS (x16) 000 Ø 160 001 Ø ...
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Zilog STAT0 RDRF OVRN PE Bit Upon Reset R/W † /DCD0 - Depending on the condition of /DCD0 Pin. †† /CTS0 Pin L H STAT1 Bit RDRF OVRN 0 0 Upon Reset R R ...
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Zilog ASCI CHANNELS CONTROL REGISTERS (Continued) TDR0 Write Only Addr 06H Figure 28. ASCI Transmit Data Register (Ch. 0) TDR1 Write Only Addr 07H ...
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Zilog ACSI TIME CONSTANT REGISTERS New Z8S180 Registers Register: ASCI0 Time Constant Low Address: 1Ah Register: ASCI0 Time Constant High Address: 1Bh CSI/O REGISTERS ...
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Zilog TIMER DATA REGISTERS TMDR0L Read/Write Addr 0CH Figure 36. Timer 0 Data Register L TMDR1L Read/Write Addr 14H Figure 37. Timer 1 Data ...
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Zilog TIMER CONTROL REGISTER TCR Bit TIF1 TIF0 Upon Reset TOC1,0 A15/TOUT FREE RUNNING COUNTER CPU CONTROL REGISTER Addr ...
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Zilog DMA REGISTERS SAR0L Read/Write Addr 20H SA7 SA0 SAR0H Read/Write Addr 21H SA15 SA8 SAR0B Read/Write Addr 22H SA19 SA16 - - - - Bits 0-3 are used for SAR0B SAR18-16 Source SM1-0 000 ext (TOUT/DREQ) 11 001 ASCI0 ...
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Zilog BCR0L Read/Write Addr 26H BC7 BCR0H Read/Write Addr 27H BC15 Figure 49. DMA 0 Byte Counter Registers IAR1B BC0 BC8 Figure 50. DMA 1 Memory ...
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Zilog DMA REGISTER DESCRIPTION Bit 7. This bit should be set to 1 only when both DMA channels are set to take their requests from the same device. If this bit is 1 (it resets to 0), the channel end ...
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Zilog DMA REGISTERS (Continued) DMODE - - Bit 1 1 Upon Reset R/W DM1, 0 Destination I/O MMOD 0 Cycle Steal Mode 1 Burst Mode ...
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Zilog DMA REGISTERS (Continued) DCNTL Bit MWI1 MWI0 Upon Reset 1 R/W R/W * MWI1 DMSi 1 0 DM1 Note using the Wait-State Generators provided in register D8, ...
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Zilog SYSTEM CONTROL REGISTERS IL Bit IL7 IL6 Upon Reset 0 R/W R/W R/W ITC Bit TRAP UFO Upon Reset 0 R/W R/W RCR Bit REFE REFW Upon Reset 1 R/W R/W CYC1 ...
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Zilog MMU REGISTERS CBR Bit CB7 CB6 Upon Reset 0 0 R/W R/W R/W BBR Bit BB6 BB7 Upon Reset 0 0 R/W R/W R/W CBAR Bit CA3 CA2 Upon Reset 1 1 R/W R/W R/W Figure 62. MMU Common/Bank ...
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Zilog SYSTEM CONTROL REGISTERS OMCR Bit M1E /M1TE Upon Reset 1 R/W R/W Notes: 1. This register should be programmed to 0x0xxxxxb (x = don't care part of Initialization the M1E bit is set to 1, ...
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Zilog CPU CONTROL REGISTER The CPU Control Register allows the programmer to select options that directly affect the CPU performance as well as controlling the STANDBY operating mode of the chip. The CPU Control Register (CCR) allows the programmer to ...
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Zilog Bit 7. Clock Divide Select. Bit 7 of the CCR allows the programmer to set the internal clock to divide the external clock by two if the bit is 0 and divide-by-one if the bit is 1. Upon reset, ...
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Zilog ON-CHIP ENHANCED SERIAL COMMUNICATIONS CONTROLLER (EMSCC) The Z80185 contains a single-channel EMSCC which features a 4-byte transmit FIFO and an 8-byte receive FIFO, this enhancement reduces the overhead required to provide data to, and get data from, the transmitter ...
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Zilog Databus CPU & DMA Bus Interface Control /INTACK Interrupt Control Transmit Logic Transmit FIFO Transmit MUX 4 Bytes Data Encoding & CRC Generation Receive and Transmit Clock ...
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Zilog EMSCC The Z80185 features a one-channel EMSCC that uses two I/O addresses: EMSCC Channel A Control I/O Address %E8 Data I/O Address %E9 Divide-by-two should be programmed when operating the Z80185 beyond 20 MHz, 5V. Note: Upon power-up, or ...
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Zilog A LocalTalk feature has been added in one EMSCC of the Z80185, operating as follows certain set of register bits are set, RTS acts as a LocalTalk Driver Enable output that operates as shown in Figure 50. ...
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Zilog EMSCC REGISTERS Write Register 0 (non-multiplexed bus mode Register Register Register Register ...
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Zilog Sync7 Sync1 Sync7 Sync3 ADR7 ADR7 Sync7 Sync5 Sync15 Sync11 0 Figure 69. Write Register Bit Functions (Continued Write Register ...
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Zilog EMSCC REGISTERS (Continued) WR' Prime Write Register Reset 0 1 Not used 1 0 Channel Reset 1 1 Force ...
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Zilog Write Register Write Register Figure 71. Write Register Bit Functions (Continued ...
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Zilog EMSCC REGISTERS (Continued) Read Register Read Register Read Register DS971850301 P R ...
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Zilog Read Register Read Register Figure 73. Read Register Bit Functions (Continued ...
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Zilog P1284 REGISTER MAP Register Name PARM Register PARC Register (asymmetric) PARC2 Register PART Register PARV Register Z80185 BIDIRECTIONAL CENTRONICS P1284 CONTROLLER The Centronics P1284 Controller can operate in either the Host or Peripheral role in Compatibility mode (host to ...
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Zilog Bidirectional Centronics Registers Reading the Parallel Controls (PARC) register allows soft- ware to sense the state of the input signals per the current mode, plus two or three status flags: Busy PError 7 6 nAutoFd nStrobe 7 6 Figure ...
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Zilog Z80185 BIDIRECTIONAL CENTRONICS P1284 CONTROLLER (Continued) Because there are five outputs in a Peripheral mode, another register, called PARC2, allows software to change the nAck line, rather than the Select line: 1=drive 1=drive Busy PError High High 7 6 ...
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Zilog A second output register has been added for PIA27-20. Writing to either the Z80181-compatible PIA 2 Data Regis- ter (address E3) or the new Alternate PIA 2 Data Register (address EE) writes to the Output Holding Register (OHR). When ...
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Zilog Z80185 BIDIRECTIONAL CENTRONICS P1284 CONTROLLER (Continued) PARM Register State Machine State Counter PARC, PARC2 Registers Host/Peripheral Control Signal Management nAck nAutoFd Busy nStrobe PError nSelectIn Select nInit nFault Figure 81. Bidirectional Centronics P1284 Controller DS971850301 ...
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Zilog Interrupts As in other Zilog peripherals, the controller includes an interrupt pending bit (IP), and an interrupt under service bit (IUS). The controller is part of an on-chip interrupt acknowl- edge daisy-chain that extends from the IEI pin, through ...
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Zilog Z80185 BIDIRECTIONAL CENTRONICS P1284 CONTROLLER (Continued) Host Compatible Mode 1. Setting this mode configures PIA27-20 as outputs re- gardless of the contents of register E2. When entering this mode, the controller sets the Idle and DREQ bits, but these ...
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Zilog In this mode, software should monitor for the condition P1284Active (nSelectIn) High, and nAutoFd Low simulta- neously. If software detects this state, it should participate in a Negotiation process. Software should read the value on PIA27-20 and set PError, ...
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Zilog Z80185 BIDIRECTIONAL CENTRONICS P1284 CONTROLLER (Continued) Peripheral Nibble Mode 1. Software shouldn’t set this mode until there is reverse data available to send. In other words, it should imple- ment the P1284 “reverse idle mode” via software in Peripheral ...
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Zilog In response to Idle, software should enter Host Negotiation mode. Thereafter, it can set HostBusy (nAutoFd) Low, to enter Reverse Idle state, or enter Host Compatible mode (reference IEEE P1284 specification), or conduct a new negotiation. If software is ...
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Zilog Z80185 BIDIRECTIONAL CENTRONICS P1284 CONTROLLER (Continued) Host ECP Forward Mode 1. After a negotiation for ECP mode, “host” software should remain in Negotiation mode so that it has com- plete control of the interface, until one of two situations ...
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Zilog Peripheral ECP Forward Modes 1. After a negotiation for ECP mode, “peripheral” software should remain in Compatibility/Negotiation mode with P1284Active (nSelectIn) High, so that it has complete control of the interface, though when it detects the host drive HostAck ...
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Zilog Z80185 BIDIRECTIONAL CENTRONICS P1284 CONTROLLER (Continued) Host ECP Reverse Modes 1. In these modes the controller configures PIA27-20 as inputs, regardless of the contents of register E2. On entry to one of these modes, the controller clears the Idle ...
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Zilog Peripheral ECP Reverse Mode 1. In this mode, as long as nReverseRequest (nInit) is Low, and P1284Active (nSelectIn) is High, the controller drives the contents of the Input/Output Register onto PIA27-20, regardless of the contents of the E2 register. ...
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Zilog Z80185 CTC, AND MISCELLANEOUS REGISTERS The following section describes miscellaneous registers that control the Z80185 configuration, including RAM/ ROM registers, Interrupt and various Status and Timer registers. Register Name WSG Chip Select Register PIA1/CTC Pin Select Register Interrupt Edge ...
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Zilog System Configuration Register This register controls a number of device-level features on the Z80185 and includes the following control bits Figure 82. System Configuration Register ...
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Zilog Z80185 PIA AND MISCELLANEOUS REGISTERS (Continued) System Configuration Register (Continued) Bit 7. Decode High I/O. If this bit after a Reset, A15-8 are not decoded for the registers for which A7-6 are 11, that ...
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Zilog Table 6. Data Bus Direction (Z185 Bus Master) I/O and Memory Transactions I/O Write I/O Read to On-Chip from On-Chip Peripherals Peripherals Z80185 Data Bus Out Z (ROME=0) Z80185 Data Bus Out Out (ROME=1) Interrupt Acknowledge Transaction Intack for ...
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Zilog Z80185 PIA AND MISCELLANEOUS REGISTERS (Continued) RAM And ROM Registers Three registers, ROMBR, RAMLBR and RAMUBR, and two pins, /ROMCS and /RAMCS, assist with decoding of ROM and RAM blocks of memory. RAMUBR (I/O Address %EA ...
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Zilog Wait State Generation (WSG) The Memory Wait Insertion field of the DCNTL register applies to all accesses to memory, and allows insertion of 0-3 wait states. In the Z80185, the WSG Chip Select Register allows individual wait state control ...
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Zilog Z80185 PIA AND MISCELLANEOUS REGISTERS (Continued) Interrupt Edge Register Interrupt Edge Register (I/O Address %DF /DCD0/CKA0 is /DCD0 1 = /DCD0/CKA0 ...
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Zilog Individual Pin Selection Between PIA1 and CTCs The assignment of the choice between PIA1 and CTC I/Os is controlled by the PIA1/CTC Pin Select Register (Figure 79). Bit 7. Reserved, and should be programmed as 0. Bits 6-4. When ...
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Zilog Z80185 PIA AND MISCELLANEOUS REGISTERS (Continued) CTC Control Registers Channel Control Byte This byte is used to set the operating modes and param- eters. Bit D0 must indicate that this is a Control Byte (Figure ...
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Zilog Addr: E4h (Ch 0) E5h (Ch 1) E6h (Ch 2) E7h (Ch 3) Control or Vector 0 Vector 1 ...
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Zilog Z80185 PIA AND MISCELLANEOUS REGISTERS (Continued) CTC Control Registers (Continued) Time Constant Before a channel can start counting, it must receive a time constant. The time constant value may be anywhere be- tween 1 and 256, with 0 indicating ...
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Zilog Watch-Dog Control Registers Two registers control WDT operations. These are WDT Master Register (WDTMR; I/O Address F0h) and the WDT Command Register (WDTCR; I/O Address F1h). WDT logic has a “double key” structure to prevent accidental disabling of the ...
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Zilog Z80185 PIA AND MISCELLANEOUS REGISTERS (Continued) Parallel Ports The Z80185 has two 8-bit bidirectional ports. Each bit is individually programmable for input or output. Each port includes two registers: the Port Direction Control Register and the Port Data Register. ...
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Zilog ELECTRICAL CHARACTERISTICS The following classification table describes pins in terms of input and output classes 10%, unless otherwise DD noted. Pin Input/Output Classification Class “O” output: Full time / totem pole Slew ...
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Zilog ELECTRICAL CHARACTERISTICS (Continued) The following table shows the characteristics of each pin in terms of the above classifications. A dash "–" in the input or output column indicates the pin does not have that function. Pin Input Class /BUSREQ ...
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Zilog PACKAGE INFORMATION 100-Pin QFP Package Diagram Z80185/Z80195 MART ERIPHERAL ONTROLLERS DS971850301 ...
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... Zilog ORDERING INFORMATION Z80185 (ROM Version) 20 MHz 33 MHz Z8018520FSC Z8018533FSC Z80195 (ROMless Version) 20 MHz 33 MHz Z8019520FSC Z8019533FSC For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired. Package Plastic Quad Flatpack Temperature +70 C Speeds: ...