KM681001B-15 Samsung semiconductor, KM681001B-15 Datasheet
KM681001B-15
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KM681001B-15 Summary of contents
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... KM681001B Document Title 128Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out. Operated at Commercial and Industrial Temperature Range. Revision History Rev . No. History Rev. 0.0 Initial release with Design Target. Rev. 1.0 Release to Preliminary Data Sheet. 1. Replace Design Target to Preliminary. Rev. 2.0 Release to Final Data Sheet. ...
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... The KM681001B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681001B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung s advanced CMOS process and designed for high-speed circuit technology ...
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... KM681001B ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... CO CO1 CO2 LZ LZ1 LZ2 HZ HZ1 HZ2 =5.0V 10%, unless otherwise noted.) CC Output Loads(B) for WHZ OW +5.0V 480 D 255 30pF* * Including Scope and Jig Capacitance KM681001B-15 Symbol Min CO LZ OLZ OHZ ...
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... Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z NOTE : WR1 WR2 TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Valid Data KM681001B-15 Symbol Min Max ...
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... KM681001B TIMING WAVEFORM OF READ CYCLE(2) Address Data out Current SB NOTES(READ CYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V ...
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... KM681001B TIMING WAVEFORM OF WRITE CYCLE(2) Address High-Z Data in Data out TIMING WAVEFORM OF WRITE CYCLE(3) Address High-Z Data in High-Z Data out (OE=Low Fixed CW( AS(4) WP1(2) t Valid Data t WHZ(6) High-Z(8) (CS = Controlled CW(3) t AS(4) t WP( Valid Data ...
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... KM681001B TIMING WAVEFORM OF WRITE CYCLE(4) Address Data in High-Z Data out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS CS going high and WE going low ; A write ends at the earliest transition CS ...
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... KM681001B PACKAGE DIMENSIONS 32-SOJ-300 #32 8.64 0.12 0.340 0.005 #1 +0.10 0.43 0.95 -0. +0.004 0.017 0.0375 -0.002 32-SOJ-400 #32 11.18 0.12 0.440 0.005 #1 +0.10 0.43 -0.05 0. +0.004 0.017 0.0375 -0.002 #17 #16 21.36 MAX 0.841 20.95 0.12 0.825 0.005 ( ( +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 #17 #16 21.36 MAX 0.841 20.95 0.12 0.825 0.005 1.30 ( 0.051 1.30 ( 0.051 +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 - 9 - PRELIMINARY CMOS SRAM Units:millimeters/Inches 6 ...