XC7300FM Xilinx, XC7300FM Datasheet - Page 7

• Manufacturer Part Number: XC7300FM
• Description: XC7300 CMOS EPLD Family
• Manufacturer: Xilinx

XC7300 EPLD Family
Output buffers, except those connected to Fast Function
Blocks, can sink 12 mA when V
Block outputs can sink 24 mA when V
puts on the XC7318 and XC7336 devices connect to
FFBs. Outputs listed as Fast Outputs (FO) on the
XC7354, XC7372, XC73108 and XC73144 devices con-
nect to FFBs.
mable input structure that can be configured as direct,
latched, or registered. The latch and flip-flop can use one
of two FastCLK signals as latch enable or clock. The two
FastCLK signals are FCLK0 and a global choice of either
FCLK1 or FCLK2. Latches are transparent when FastCLK
is High, and flip-flops clock on the rising edge of FastCLK.
The flip-flop includes an active-low clock enable, which
when High, holds the present state of the flip-flop and
inhibits response to the input signal. The clock enable
source is one of two global Clock Enable signals (CE0
and CE1). An additional configuration option is polarity
inversion for each input signal.
3.3 V or 5 V Interface Configuration
XC7300 devices can be used in systems with two differ-
ent supply voltages: 3.3 V and 5 V. Each XC7300 device
has separate V
input buffers (V
V
ply, while V
depending on the output interface requirement.
When V
TTL levels, and thus compatible with 3.3 V and 5 V logic.
The output High levels are also TTL compatible. When
V
TTL levels, and the outputs pull up to the 3.3 V rail. This
makes the XC7300 ideal for interfacing directly to 3.3 V
components. In addition, the output structure is designed
so that the I/O can also safely interface to a mixed 3.3 V
and 5 V bus.
Power-On Characteristics/Master Reset
The XC7300 device undergoes a short internal initializa-
tion sequence upon device powerup. During this time
(t
configured from its internal EPROM array and all registers
are initialized. If the MR pin is tied to V
tion sequence is completely transparent to the user and is
completed in t
MR is held low while the device is powering up, the inter-
nal initialization sequence begins and outputs will remain
3-stated until the sequence is complete and MR is
brought High. V
initialization sequence is performed correctly.
Each signal input to the chip is connected to a program-
RESET
CCINT
CCIO
is connected to 3.3 V, the input thresholds are still
), the outputs remain 3-stated while the device is
must always be connected to a nominal 5 V sup-
CCIO
CCIO
is connected to 5 V, the input thresholds are
RESET
CC
CC
CCINT
may be connected to either 3.3 V or 5 V,
connections to the internal logic and
rise must be monotonic to insure the
after V
) and to the I/O drivers (V
CCINT
CCIO
has reached 4.75 V. If
= 5 V. Fast Function
CCINT
CCIO
, the initializa-
= 5 V. All out-
CCIO
).
2-7
For additional flexibility, the MR pin is provided so the
EPLD can be reinitialized after power is applied. On the
falling edge of MR, all outputs become 3-stated and the
initialization sequence is started. The outputs will remain
3-stated until the internal initialization sequence is com-
plete and MR is brought High. The minimum MR pulse
with is t
t
During the initialization sequence, all input registers or
latches are preloaded High and all FB and FFB Macrocell
registers are preloaded to a known state. For FFB Macro-
cell registers where the Set/Reset product-term is
defined, the preload is accomplished by asserting the
product-term shortly before the end of the initialization
sequence. When the Set/Reset product-term is defined
and configured as Reset, the register preload value is
Low. When the Set/Reset product-term is defined and
configured as a Set, the register preload value is High.
For FFB Macrocell registers where the Set/Reset prod-
uct-term is not used, the register preload value is High.
For FB Macrocell registers, the preload value is defined
by a separate preload configuration bit, independent of
the Set and Reset product-terms. The value of this pre-
load configuration bit is determined by the schematic cap-
ture library or in the user’s design. If not specified, the
register preload value is Low.
Power Management
The XC7300 family of devices feature a power-manage-
ment scheme which permits non-speed-critical paths of a
design to be operated at reduced power. Overall power
dissipation is often reduced significantly, since, in most
systems only a small part is speed critical.
Macrocells can individually be specified for high perfor-
mance or low power operation by adding attributes to the
logic schematic, or declaration statements to the behav-
ioral description. To further reduce power dissipation,
unused Function Blocks are turned off and unused Mac-
rocells in used Function Blocks are configured for low
power operation.
Erasure Characteristics
In windowed packages, the content of the EPROM array
can be erased by exposure to ultraviolet light of wave-
lengths of approximately 4000 Å. The recommended era-
sure time is approximately 1 hr. when the device is placed
within 1 in. of an ultraviolet lamp with a 12,000 W/cm
power rating. To prevent unintentional exposure, place
opaque labels over the device window.
When the device is exposed to high intensity UV light for
much longer periods, permanent damage can occur. The
RESET
, the outputs will become active after t
WMR
. If MR is brought high after t
WMR
RESET
, but before
.
2