PALCE20V8H-25PC/4 Lattice Semiconductor, PALCE20V8H-25PC/4 Datasheet - Page 17
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PALCE20V8H-25PC/4
Manufacturer Part Number
PALCE20V8H-25PC/4
Description
EE CMOS 24-Pin Universal Programmable Array Logic
Manufacturer
Lattice Semiconductor
Datasheet
1.PALCE20V8H-25PC4.pdf
(27 pages)
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CAPACITANCE
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
3. t
C IN
C OUT
t
t
t
t
t
t
f
t
t
t
t
PD
S
H
CO
WL
WH
MAX
PZX
PXZ
EA
ER
Parameter
Parameter
Symbol
Symbol
capacitance may be affected.
frequency may be affected.
t
CF
CF
is a calculated value and is not guaranteed. t
= 1/f
MAX
Input or Feedback to Combinatorial Output
Setup Time from Input or Feedback to Clock
Hold Time
Clock to Output
Clock Width
Maximum
Frequency
(Note 2)
OE to Output Enable
OE to Output Disable
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
Input Capacitance
Output Capacitance
(internal feedback) – t
Parameter Description
1
LOW
HIGH
External Feedback
Internal Feedback
(f
No Feedback
CNT
Parameter Description
)
S
.
1/(t
1/(t
1/(t
PALCE20V8H-15/25 Q-20/25 (ind)
S
S
WH
+t
+t
+t
CO
CF
) (Note 3)
WL
)
CF
)
can be found using the following equation:
V IN = 2.0 V
V OUT = 2.0 V
Min
45.5
62.5
12
50
0
8
8
-15
Test Conditions
Max
15
10
15
15
15
15
V CC = 5.0 V, T A = 25
f = 1 MHz
Min
41.6
45.4
50.0
13
10
10
0
-20
Max
20
11
18
18
18
18
°
C,
Min
41.6
15
12
12
37
40
0
-25
Max
Typ
25
12
20
20
25
25
5
8
Unit
Unit
MHz
MHz
MHz
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
17