LTC4266 LINER [Linear Technology], LTC4266 Datasheet - Page 12

• Manufacturer Part Number: LTC4266
• Description: Quad IEEE 802.3at Power over Ethernet Controller
• Manufacturer: LINER [Linear Technology]

PIN FUNCTIONS
LTC4266
12
RESET: Chip Reset, Active Low. When the RESET pin is
low, the LTC4266 is held inactive with all ports off and all
internal registers reset to their power-up states. When
RESET is pulled high, the LTC4266 begins normal opera-
tion. RESET can be connected to an external capacitor
or RC network to provide a power turn-on delay. Internal
filtering of the RESET pin prevents glitches less than 1µs
wide from resetting the LTC4266. Internally pulled up to
V
MID: Midspan Mode Input. When high, the LTC4266 acts
as a midspan device. Internally pulled down to DGND.
INT: Interrupt Output, Open Drain. INT will pull low when
any one of several events occur in the LTC4266. It will
return to a high impedance state when bits 6 or 7 are set
in the Reset PB register (1Ah). The INT signal can be used
to generate an interrupt to the host processor, eliminating
the need for continuous software polling. Individual INT
events can be disabled using the Int Mask register (01h).
See LTC4266 Software Programming documentation for
more information. The INT pin is only updated between
I
SCL: Serial Clock Input. High impedance clock input for
the I
used.
SDAOUT: Serial Data Output, Open Drain Data Output for
the I
to implement the bidirectional SDA function to simplify
optoisolation of the I
bidirectional SDA pin, tie SDAOUT and SDAIN together.
SDAOUT should be grounded or left floating if not used.
See Applications Information for more information.
SDAIN: Serial Data Input. High impedance data input for
the I
to implement the bidirectional SDA function to simplify
optoisolation of the I
bidirectional SDA pin, tie SDAOUT and SDAIN together.
SDAIN must be tied high if not used. See Applications
Information for more information.
2
DD
C transactions.
.
2
2
2
C serial interface bus. SCL must be tied high if not
C Serial Interface Bus. The LTC4266 uses two pins
C serial interface bus. The LTC4266 uses two pins
2
2
C bus. To implement a standard
C bus. To implement a standard
AD3: Address Bit 3. Tie the address pins high or low to set
the I
address will be 010A
AD2: Address Bit 2. See AD3.
AD1: Address Bit 1. See AD3.
AD0: Address Bit 0. See AD3.
NC, DNC: All pins identified with “NC” or “DNC” must be
left unconnected.
DGND: Digital Ground. DGND is the return for the V
supply.
V
relative to DGND. V
the LTC4266 with at least a 0.1µF capacitor.
SHDN1: Shutdown Port 1, Active Low. When pulled low,
SHDN1 shuts down port 1, regardless of the state of the
internal registers. Pulling SHDN1 low is equivalent to set-
ting the Reset Port 1 bit in the Reset Pushbutton register
(1Ah). Internal filtering of the SHDN1 pin prevents glitches
less than 1µs wide from reseting the port. Internally pulled
up to V
SHDN2: Shutdown Port 2, Active Low. See SHDN1.
SHDN3: Shutdown Port 3, Active Low. See SHDN1.
SHDN4: Shutdown Port 4, Active Low. See SHDN1.
AGND: Analog Ground. AGND is the return for the V
supply.
SENSE4: Port 4 Current Sense Input. SENSE4 monitors
the external MOSFET current via a 0.5Ω or 0.25Ω sense
resistor between SENSE4 and V
across the sense resistor exceeds the overcurrent detection
threshold V
the voltage across the sense resistor reaches the current
limit threshold V
maintain constant current in the external MOSFET. See
Applications Information for further details. If the port is
unused, the SENSE4 pin must be tied to V
DD
: Logic Power Supply. Connect to a 3.3V power supply
2
C serial address to which the LTC4266 responds. This
DD
.
CUT
, the current limit fault timer counts up. If
LIM
DD
, the GATE4 pin voltage is lowered to
3
A
2
must be bypassed to DGND near
A
1
A
0
b. Internally pulled up to V
EE
. Whenever the voltage
EE
.
4266fb
DD
DD
EE
.