CY7B9945V-2AIT CYPRESS [Cypress Semiconductor], CY7B9945V-2AIT Datasheet - Page 3

• Manufacturer Part Number: CY7B9945V-2AIT
• Description: High Speed Multi-phase PLL Clock Buffer
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Definitions
Document Number: 38-07336 Rev. *F
34
40,39,
36,37
38
42
28,18,
35,17, 2,
1
19,26
14,12,
13,3
29
50,51
48,46,
32,30,
5,7,8,10
, 20,22
44
52
25
6,9,21,
31, 45,
47
16,27,
41
4,11,15,
23,24,
33,43,4
9
Pin
FS
REFA+, REFA-
REFB+, REFB-
REFSEL
FBK
1F[0:3], 2F[0:1]
DIS[1:2]
[1:2]DS[0:1]
FBF0
FBDS[0:1]
1Q[0:3], 2Q[0:5]
QF
LOCK
MODE
VCCN
VCCQ
GND
Name
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
IO
Three level
Three level
Three level
Three level
Three level
Three level
LVDIFF
LVTTL/
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
PWR
PWR
PWR
Type
Input
Input
Input
Input
Input
Input
PRELIMINARY
Frequency Select. This input must be set according to the nominal frequency
(f
Reference Inputs. These inputs can operate as differential PECL or
single-ended TTL reference inputs to the PLL. When operating as a
single-ended LVTTL input, the complementary input is left open.
Reference Select Input. The REFSEL input controls the configuration of
reference input When LOW, it uses the REFA pair as the reference input. When
HIGH, it uses the REFB pair as the reference input. This input has an internal
pull down.
Feedback Input Clock. The PLL operates such that the rising edges of the
reference and feedback signals are aligned in phase and frequency. This pin
provides the clock output QF feedback to the phase detector.
Output Phase Function Select. Each pair determines the phase of the
respective bank of outputs. See
Output Disable. Each input controls the state of the respective output bank.
When HIGH, the output bank is disabled to HOLD-OFF or High-Z state; the
disable state is determined by MODE. When LOW, outputs 1Q[0:3] and 2Q[0:5]
are enabled. See
Output Divider Function Select. Each pair determines the divider ratio of the
respective bank of outputs. See
Feedback Output Phase Function Select. This input determines the phase of
the QF output. See
Feedback Output Divider Function Select. This input determines the divider
ratio of the QF output. See
Clock Outputs with Adjustable Phases and f
frequencies and phases are determined by [1:2]DS[0:1], and 1F[0:3] and
2F[0:1], respectively. See
Feedback Clock Output. This output is connected to the FBK input. The output
frequency and phase are determined by FBDS[0:1] and FBF0, respectively. See
Table 3
PLL Lock Indicator. When HIGH, this output indicates that the internal PLL is
locked to the reference signal. When LOW, it indicates that the PLL is attempting
to acquire lock
This pin determines the clock outputs’ disable state. When this input is
HIGH, the clock outputs disables to high impedance state (High-Z). When this
input is LOW, the clock outputs disables to HOLD-OFF mode. When in MID, the
device enters factory test mode.
Power Supply for the Output Buffers
Power Supply for the Internal Circuitry
Device Ground
NOM
). See
and
Table 1.
Table
Table
4.
Table
5.
3.
Table 3
Table
Table
Table
Description
4.
and
3.
4.
Table
4.
NOM
Divide Ratios. The output
CY7B9945V
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