CY7C006-15JC CYPRESS [Cypress Semiconductor], CY7C006-15JC Datasheet - Page 8

• Manufacturer Part Number: CY7C006-15JC
• Description: 16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Read Timing with Port-to-Port Delay (M/S=L)
Write Cycle No. 1: OE Three-State Data I/Os (Either Port)
Notes:
DATA OUT
19. BUSY = HIGH for the writing port.
20. CE
21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
23. R/W must be HIGH during all address transitions.
SEM OR CE
ADDRESS
ADDRESS
ADDRESS
DATA IN
DATA
DATA IN
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
the bus for the required t
specified t
R/W
L
R/W
OUTL
OE
= CE
R
R
R
PWE
R
L
= LOW.
.
SD
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the
t
SA
(continued)
t
HZOE
[19, 20]
t
SCE
MATCH
t
MATCH
AW
HIGH IMPEDANCE
t
WC
[21, 22, 23]
t
WC
t
8
PWE
t
PWE
t
WDD
PWE
or (t
t
SD
HZWE
t
VALID
DATA VALID
SD
+ t
SD
) to allow the I/O drivers to turn off and data to be placed on
t
DDD
t
t
HD
HD
t
LZOE
t
HA
CY7C006
CY7C016
VALID
C006-12
C006-13