CY7C0241 CYPRESS [Cypress Semiconductor], CY7C0241 Datasheet - Page 13

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CY7C0241

Manufacturer Part Number
CY7C0241
Description
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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Document #: 38-06035 Rev. *C
Switching Waveforms
Notes:
36. CE = HIGH for the duration of the above timing (both write and read cycle).
37. I/O
38. Semaphores are reset (available to both ports) at cycle start.
39. If t
Timing Diagram of Semaphore Contention
Semaphore Read After Write Timing, Either Side
SPS
0R
A
A
A
0R
0L
= I/O
0
is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
SEM
SEM
SEM
–A
R/W
I/O
R/W
R/W
–A
–A
OE
0L
2
2L
2R
0
R
L
= LOW (request semaphore); CE
L
R
t
SA
(continued)
VALID ADRESS
t
AW
R
= CE
WRITE CYCLE
t
t
PWE
SCE
L
t
SD
DATA
= HIGH.
t
MATCH
SPS
MATCH
[37, 38, 39]
t
IN
HA
VALID
[36]
t
HD
t
SWRD
t
SOP
t
SOP
READ CYCLE
t
AA
VALID ADRESS
t
DOE
t
ACE
DATA
OUT
CY7C024/0241
CY7C025/0251
VALID
t
OHA
Page 13 of 21

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