MT42C4256C-10/883C AUSTIN [Austin Semiconductor], MT42C4256C-10/883C Datasheet - Page 7

• Manufacturer Part Number: MT42C4256C-10/883C
• Description: 256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM
• Manufacturer: AUSTIN [Austin Semiconductor]

RANDOM-ACCESS-OPERATION FUNCTIONS
NOTES:
1. In persistent write-per-bit function, W must be high during the refresh cycle.
2. DQ0–DQ3 are latched on the later of W or CAS falling edge. Col Mask = H: Write to address/column location enabled.
LEGEND:
H = High
L = Low
X = Don’t care
RANDOM-ACCESS OPERATION
the “Random-Access-Operation Function” table and described
in the following sections.
ENHANCED PAGE-MODE
access by keeping the same row address while selecting
random column addresses. This mode eliminates the time
required for row address setup-and-hold and address
multiplex. The maximum RAS\ low time and the CAS\ page cycle
time used determine the number of columns that can be
accessed.
page mode allows the SMJ44C251B/MT42C4256 to operate at a
higher data bandwidth. Data retrieval begins as soon as the
column address is valid rather than when CAS\ transitions low.
A valid column address can be presented immediately after
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
CBR Refresh
Load and use write mask,
Write data to DRAM
Load and use write mask,
Block write to DRAM
Persistent write-per-bit,
Write data to DRAM
Persistent write-per-bit,
Block write to DRAM
Normal DRAM read/write
(nonmasked)
Block write to DRAM
(nonmasked)
Load write mask
Load color register
DQ Mask = H: Write to I/O enabled
The random-access operation functions are summarized in
Enhanced page-mode operation allows faster memory
Unlike conventional page-mode operation, the enhanced
FUNCTION
Austin Semiconductor, Inc.
CAS\
H
H
H
H
H
H
H
H
L
TRG\
H
H
H
H
H
H
H
H
X
RAS\ FALL
W\
H
H
H
H
X
L
L
L
L
1
7
DSF
row-address hold time has been satisfied, usually well in ad-
vance of the falling edge of CAS\. In this case, data can be
obtained after t
(access time from column address) has been satisfied.
REFRESH
SMJ44C251B/MT42C4256: RAS\-only refresh, CBR refresh, and
hidden refresh.
RAS\-ONLY REFRESH
once every 8 ms to retain data. Unless CAS\ is applied, the
output buffers are in the high-impedance state, so the RAS\-
only refresh sequence avoids any output during refresh. Exter-
nally generated addresses must be supplied during RAS-only
refresh. Strobing each of the 512 row addresses with RAS causes
H
H
H
H
X
L
L
L
L
There are three types of refresh available on the
A refresh operation must be performed to each row at least
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SE\
X
X
X
X
X
X
X
X
X
a(C)
FALL
CAS\
DSF
max (access time from CAS low), if t
X
H
H
H
H
L
L
L
L
Refresh
Refresh
RAS\
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Row
Row
Row
Row
Row
Row
X
ADDRESS
SMJ44C251B
Blk Addr
Blk Addr
Blk Addr
A2-A8
A2-A8
A2-A8
CAS\
Addr
Addr
Addr
Col
Col
Col
MT42C4256
X
X
X
VRAM
VRAM
VRAM
VRAM
VRAM
RAS\ CAS\
Mask
Mask
DQ0 - DQ3
DQ
DQ
X
X
X
X
X
X
X
(continued)
a(CA)
Mask
Mask
Mask
Mask
Color
Valid
Valid
Valid
Data
Data
Data
Data
Col
Col
Col
DQ
W\
X
max
2