CY7C1021D CYPRESS [Cypress Semiconductor], CY7C1021D Datasheet - Page 6

• Manufacturer Part Number: CY7C1021D
• Description: 1-Mbit (64K x 16) Static RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Data Retention Characteristics
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
Read Cycle No. 2 (OE Controlled)
Notes
Document #: 38-05462 Rev. *E
V
I
t
t
13. Full device operation requires linear V
14. Device is continuously selected. OE, CE, BHE and/or BLE = V
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
Parameter
CCDR
CDR
R
DATA OUT
CURRENT
ADDRESS
DR
BHE, BLE
[13]
DATA OUT
ADDRESS
SUPPLY
[4]
V
CE
OE
CC
V
CE
CC
V
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
CC
for Data Retention
PREVIOUS DATA VALID
HIGH IMPEDANCE
Description
t
t
LZCE
PU
CC
[15, 16]
ramp from V
t
ACE
t
t
LZBE
t
DBE
LZOE
t
DOE
(Over the Operating Range)
t
50%
OHA
t
CDR
4.5V
DR
to V
t
IL
[14, 15]
CC(min)
AA
.
V
V
IN
CC
> 50 µs or stable at V
t
RC
> V
= V
DATA RETENTION MODE
CC
DR
– 0.3 V or V
= 2.0 V, CE > V
t
RC
RC
V
DR
>
Conditions
CC(min)
2V
IN
DATA VALID
< 0.3 V
> 50 µs.
CC
– 0.3 V,
Industrial
Automotive
t
HZOE
DATA VALID
4.5V
t
R
t
t
HZCE
HZBE
t
PD
Min
50%
2.0
t
CY7C1021D
RC
0
IMPEDANCE
HIGH
Max
15
Page 6 of 11
3
Unit
mA
mA
I
I
ns
ns
V
CC
SB
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