ICS83948AYI-147 ICST [Integrated Circuit Systems], ICS83948AYI-147 Datasheet - Page 7

• Manufacturer Part Number: ICS83948AYI-147
• Description: LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
• Manufacturer: ICST [Integrated Circuit Systems]

W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
83948AYI-147
R
I
CLK I
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
CLK/nCLK I
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
NPUTS
ECOMMENDATIONS FOR
IRING THE
NPUT
:
:
ONTROL
NPUT
D
Integrated
Circuit
Systems, Inc.
IFFERENTIAL
:
P
INS
:
U
NUSED
I
F
NPUT TO
IGURE
Single Ended Clock Input
I
1. S
NPUT AND
A
A
www.icst.com/products/hiperclocks.html
PPLICATION
CCEPT
INGLE
O
E
D
C1
0.1u
S
NDED
UTPUT
V_REF
INGLE
IFFERENTIAL
DD
/2 is
S
IGNAL
P
E
7
INS
I
NDED
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
NFORMATION
O
LVCMOS O
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
D
1K
R1
1K
R2
UTPUTS
RIVING
VDD
L
-
TO
EVELS
-LVCMOS/LVTTL F
D
CLK
nCLK
:
IFFERENTIAL
UTPUT
:
I
NPUT
DD
ICS83948I-147
= 3.3V, V_REF should be 1.25V
L
OW
S
ANOUT
KEW
REV. B NOVEMBER 21, 2005
, 1-
B
TO
UFFER
-12