M29DW640F70N1 NUMONYX [Numonyx B.V], M29DW640F70N1 Datasheet - Page 17

• Manufacturer Part Number: M29DW640F70N1
• Description: 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
• Manufacturer: NUMONYX [Numonyx B.V]

M29DW640F
3
3.1
3.2
3.3
3.4
Bus operations
There are five standard bus operations that control the device. These are Bus Read
(Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby.
Using the multiple bank architecture of the M29DW640F, while programming or erasing is
underway in one group of banks (from 1 to 3), reading can be conducted in any of the other
banks. Write operations are only allowed in one bank at a time.
See
on Chip Enable, Write Enable, and Reset pins are ignored by the memory and do not affect
bus operations.
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. To speed up the read operation the memory array can be read in Page mode
where data is internally read and stored in a page buffer. The Page has a size of 8 Words
and is addressed by the address inputs A0-A2.
A valid Bus Read operation involves setting the desired address on the Address Inputs,
applying a Low signal, V
High, V
waveforms
for details of when the output becomes valid.
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the whole Bus Write operation. See
and
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
Standby
When Chip Enable is High, V
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, I
Standby current level see
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I
Table 17
Table 4
IH
. The Data Inputs/Outputs will output the value, see
,
Figure 11: Page Read AC waveforms
and
and
Table 5
CC3
Table 18
, for Program or Erase operations until the operation completes.
, Bus operations, for a summary. Typically glitches of less than 5ns
IL
, to Chip Enable and Output Enable and keeping Write Enable
Table 15: DC characteristics
, Write AC characteristics, for details of the timing requirements.
IH
CC2
, the memory enters Standby mode and the Data
, Chip Enable should be held within V
Figure 12
, and
and
.
Table 16: Read AC characteristics
Figure 13
Figure 10: Random Read AC
, Write AC waveforms,
CC
± 0.2V. For the
Bus operations
17/74
IH
IH
,
,
.