CY7C132-35DMB CYPRESS [Cypress Semiconductor], CY7C132-35DMB Datasheet - Page 8

• Manufacturer Part Number: CY7C132-35DMB
• Description: 2K x 8 Dual-Port Static RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06031 Rev. *C
Switching Waveforms
Write Cycle No.1 (OE Three-States Data I/Os—Either Port)
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
Notes:
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
ADDRESS
ADDRESS
and for data to be placed on the bus for the required t
DATA
DATA
D
D
R/W
OUT
R/W
OUT
OE
CE
CE
IN
IN
t
HZOE
(continued)
t
SA
t
SA
SD
.
t
SCE
t
SCE
t
AW
t
AW
t
HZWE
t
WC
t
WC
[14, 22]
[14, 23]
t
HIGH IMPEDANCE
PWE
t
PWE
DATA VALID
t
SD
PWE
HIGH IMPEDANCE
or t
t
SD
HZWE
DATA VALID
+ t
SD
to allow the data I/O pins to enter high impedance
t
HD
t
HD
t
LZWE
t
t
HA
CY7C132/CY7C136
CY7C142/CY7C146
HA
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