CY7C1325-50AC CYPRESS [Cypress Semiconductor], CY7C1325-50AC Datasheet

CY7C1325-50AC

Manufacturer Part Number

CY7C1325-50AC

Description

256K x 18 Synchronous 3.3V Cache RAM

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY7C1325-50AC.pdf (16 pages)

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Features

Selection Guide

Cypress Semiconductor Corporation

Maximum Access Time (ns)

Maximum Operating Current (mA)

Maximum Standby Current (mA)

Intel and Pentium are registered trademarks of Intel Corporation.

• Supports 117-MHz microprocessor cache systems with

• 256K by 18 common I/O

• Fast clock-to-output times

• Two-bit wrap-around counter supporting either inter-

• Separate processor and controller address strobes pro-

• Synchronous self-timed write

• Asynchronous output enable

• I/Os capable of 2.5–3.3V operation

• JEDEC-standard pinout

• 100-pin TQFP packaging

• ZZ “sleep” mode

Logic Block Diagram

zero wait states

leaved or linear burst sequence

vides direct interface with the processor and external

cache controller

— 7.5 ns (117-MHz version)

ADSP

ADSC

ADV

[17:0]

BWE

CLK

•

MODE

3901 North First Street

) 2

CLR

CLK

BYTEWRITE

REGISTERS

BYTEWRITE

REGISTERS

DQ[15:8]

COUNTER

CONTROL

ADDRESS

DQ[7:0]

ENABLE

SLEEP

BURST

7C1325-117

10.0

350

7.5

Functional Description

The CY7C1325 is a 3.3V, 256K by 18 synchronous cache

RAM designed to interface with high-speed microprocessors

with minimum glue logic. Maximum access delay from clock

rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-

tures the first address in a burst and increments the address

automatically for the rest of the burst access.

The CY7C1325 allows both an interleaved or linear burst se-

quences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst

sequence. Burst accesses can be initiated with the Processor

Address Strobe (ADSP) or the Cache Controller Address

Strobe (ADSC) inputs. Address advancement is controlled by

the Address Advancement (ADV) input.

A synchronous self-timed write mechanism is provided to sim-

plify the write interface. A synchronous chip enable input and

an asynchronous output enable input provide easy control for

bank selection and output three-state control.

•

7C1325-100

San Jose

256K x 18 Synchronous

10.0

325

8.0

•

3.3V Cache RAM

7C1325-80

CA 95134

10.0

300

8.5

256K X 18

MEMORY

ARRAY

CY7C1325

•

CLK

7C1325-50

408-943-2600

REGISTERS

May 10, 2000

INPUT

11.0

10.0

250

[15:0]

[1:0]

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