IS61C632A ICSI [Integrated Circuit Solution Inc], IS61C632A Datasheet - Page 4

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IS61C632A

Manufacturer Part Number
IS61C632A
Description
32K x 32 SYNCHRONOUS PIPELINED STATIC RAM
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet

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IS61C632A
4
TRUTH TABLE
OPERATION
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
PARTIAL TRUTH TABLE
FUNCTION
READ
READ
WRITE Byte 1
WRITE All Bytes
WRITE All Bytes
LOW. WRITE=H means all byte write enable signals are HIGH.
throughout the input data hold time.
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
GW
H
H
H
X
L
ADDRESS
External
External
External
Current
Current
External
External
Current
Current
Current
Current
USED
BWE
None
None
None
None
None
Next
Next
Next
Next
Next
Next
H
X
X
L
L
BW1
H
X
L
L
X
CE1
CE1
CE1
CE1
CE1
H
L
L
L
L
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
BW2
X
H
H
X
L
CE2
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
BW3 BW4
H
H
X
L
X
CE3
CE3
CE3
CE3
CE3
X
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
H
H
L
X
ADSP
ADSP
ADSP ADSC
ADSP
ADSP
H
H
H
H
H
H
H
H
H
H
H
X
L
X
X
X
X
X
X
L
L
L
ADSC
ADSC
ADSC
ADSC
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
ADV
ADV
ADV
ADV WRITE
ADV
Integrated Circuit Solution Inc.
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
X
L
L
L
L
L
L
WRITE
WRITE
WRITE
WRITE
X
H
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
OE
OE
OE
OE
OE
H
H
X
X
X
X
X
X
H
H
X
X
H
H
X
X
L
L
L
L
L
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
SSR001-0B
DQ
Q
D
Q
Q
Q
D
Q
Q
D
D
D

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