ICS8533AG-01 ICST [Integrated Circuit Systems], ICS8533AG-01 Datasheet

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ICS8533AG-01

Manufacturer Part Number
ICS8533AG-01
Description
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet

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B
8533AG-01
G
The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL, CML,
or SSTL input levels. The clock enable is internally synchro-
nized to eliminate runt pulses on the outputs during asynchro-
nous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8533-01 ideal for those applications demanding
well defined performance and repeatability.
HiPerClockS™
,&6
LOCK
ENERAL
CLK_SEL
CLK_EN
nPCLK
PCLK
nCLK
CLK
D
The ICS8533-01 is a low skew, high perfor-
mance 1-to-4 Differential-to-3.3V LVPECL fanout
buffer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from ICS.
The ICS8533-01 has two selectable clock inputs.
IAGRAM
D
ESCRIPTION
0
1
D
LE
Q
www.icst.com/products/hiperclocks.html
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
D
IFFERENTIAL
1
F
P
4 differential 3.3V LVPECL outputs
Selectable CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, HSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency up to 650MHz
Translates any single-ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 1.4ns (maximum)
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
EATURES
IN
A
SSIGNMENT
6.5mm x 4.4mm x 0.92mm Package Body
-
TO
-3.3V LVPECL F
CLK_SEL
CLK_EN
nPCLK
PCLK
nCLK
CLK
V
V
nc
nc
CC
EE
20-Lead TSSOP
ICS8533-01
G Package
Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
L
ICS8533-01
OW
Q0
nQ0
V
Q1
nQ1
Q2
nQ2
V
Q3
nQ3
CC
CC
ANOUT
S
KEW
REV. B JULY 16, 2001
, 1-
B
UFFER
TO
-4

Related parts for ICS8533AG-01

ICS8533AG-01 Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS8533- low skew, high perfor- ,&6 mance 1-to-4 Differential-to-3.3V LVPECL fanout HiPerClockS™ buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8533-01 has two selectable clock ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

T 3A ABLE ONTROL NPUT UNCTION ...

Page 4

BSOLUTE AXIMUM ATINGS Supply Voltage, V CCx Inputs Outputs Package Thermal Impedance, JA Storage Temperature, T STG Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ...

Page 5

T 4D. LVPECL DC C ABLE HARACTERISTICS ...

Page 6

PARAMETER MEASUREMENT INFORMATION V CC LVPECL -1.3V ± 0.135V CLK, PCLK nCLK, nPCLK nQx Qy nQy 8533AG- -3.3V LVPECL F IFFERENTIAL TO Qx nQx F 2 ...

Page 7

Clock Inputs and Outputs F CLK, PCLK nCLK, nPCLK nQ0 - nQ3 CLK, PCLK, Qx nCLK, nPCLK, nQx 8533AG- IFFERENTIAL TO 80 IGURE NPUT AND UTPUT ISE ...

Page 8

W D IRING THE IFFERENTIAL Figure 8 shows how the differential input can be wired to accept single end levels. The reference voltage V_REF ~ generated by the bias resistors R1, R2 and C1. This bias circuit ...

Page 9

This section provides information on power dissipation and junction temperature for the ICS8XXX. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8XXX is the sum of the core power plus the power ...

Page 10

Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8. F IGURE T o calculate worst case power dissipation into the ...

Page 11

ABLE VS IR LOW ABLE Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to ...

Page 12

ACKAGE UTLINE UFFIX T ABLE Reference Document: JEDEC Publication 95, MS-153 8533AG- IFFERENTIAL ACKAGE IMENSIONS ...

Page 13

ABLE RDERING NFORMATION ...

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