ICS8533AG-11 ICST [Integrated Circuit Systems], ICS8533AG-11 Datasheet

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ICS8533AG-11

Manufacturer Part Number
ICS8533AG-11
Description
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet
B
G
able differential clock or crystal inputs. The CLK, nCLK pair
can accept most standard differential input levels. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8533-11 ideal for those applications demand-
ing well defined performance and repeatability.
8533AG-11
HiPerClockS™
,&6
LOCK
ENERAL
CLK_SEL
CLK_EN
XTAL1
XTAL2
nCLK
CLK
D
The ICS8533-11 is a low skew, high performance
1-to-4 Crystal Oscillator/Differential-to-3.3V
LVPECL fanout buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8533-11 has select-
IAGRAM
D
ESCRIPTION
0
1
D
LE
Q
www.icst.com/products/hiperclocks.html
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
D
IFFERENTIAL
1
P
F
L
4 differential 3.3V LVPECL outputs
Selectable CLK, nCLK or crystal inputs
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency up to 650MHz
Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 2ns (maximum)
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
EATURES
IN
OW
A
SSIGNMENT
S
-
TO
KEW
6.5mm x 4.4mm x 0.92 Package Body
-3.3V LVPECL F
CLK_SEL
CLK_EN
, 1-
XTAL1
XTAL2
nCLK
CLK
V
V
nc
nc
CC
20-Lead TSSOP
EE
TO
ICS8533-11
G Package
-4, C
Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RYSTAL
ICS8533-11
Q0
nQ0
V
Q1
nQ1
Q2
nQ2
V
Q3
nQ3
CC
CC
ANOUT
O
REV. D JULY 16, 2001
SCILLATOR
B
UFFER
/

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ICS8533AG-11 Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS8533- low skew, high performance ,&6 1-to-4 Crystal Oscillator/Differential-to-3.3V HiPerClockS™ LVPECL fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8533-11 has select- able differential ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

T 3A ABLE ONTROL NPUT UNCTION ...

Page 4

BSOLUTE AXIMUM ATINGS Supply Voltage, V CCx Inputs Outputs Package Thermal Impedance, JA Storage Temperature, T STG Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ...

Page 5

T 4D. LVPECL DC C ABLE HARACTERISTICS ...

Page 6

P ARAMETER V CC LVPECL -1.3V ± 0.135V CLK nCLK V EE REV. D JULY 16, 2001 KEW D - -3.3V LVPECL F IFFERENTIAL EASUREMENT ...

Page 7

Qx nQx Qy nQy 20% Clock Inputs and Outputs CLK nCLK nQ0 - nQ3 CLK nCLK, nQ0 - nQ3 8533AG- KEW D - IFFERENTIAL TO tsk( ...

Page 8

C O RYSTAL A crystal can be characterized for either series or parallel mode operation. The ICS8533-11 and ICS8535-11 fanout buffers have built-in crystal oscillator circuits that can accept either a series or parallel crystal without additional components. The frequency ...

Page 9

IGURE 100 -20 -40 -60 -80 -100 IGURE REQUENCY 8533AG- KEW ...

Page 10

IGURE RYSTAL W D IRING THE IFFERENTIAL Figure 12 shows how the differential input can be wired to accept single ended levels. The reference voltage ...

Page 11

This section provides information on power dissipation and junction temperature for the ICS8533-11. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8533-11 is the sum of the core power plus the power ...

Page 12

Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8. F IGURE T o calculate worst case power dissipation into the ...

Page 13

ABLE VS IR LOW ABLE q Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains ...

Page 14

ACKAGE UTLINE UFFIX REV. D JULY 16, 2001 KEW D - -3.3V LVPECL F IFFERENTIAL ABLE ACKAGE IMENSIONS ...

Page 15

T 10 ABLE RDERING NFORMATION ...

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